1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Mediatek Video Decode Accelerator With Multi Hardware
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities. Required
16  parent and child device node.
17
18  About the Decoder Hardware Block Diagram, please check below:
19
20    +------------------------------------------------+-------------------------------------+
21    |                                                |                                     |
22    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
23    |            ||             ||                   |                     ||              |
24    +------------||-------------||-------------------+---------------------||--------------+
25                 ||     lat     ||                   |               core workqueue  <parent>
26    -------------||-------------||-------------------|---------------------||---------------
27                 ||<------------||----------------HW index---------------->||        <child>
28                 \/             \/                                         \/
29               +-------------------------------------------------------------+
30               |                          enable/disable                     |
31               |                 clk     power    irq    iommu               |
32               |                   (lat/lat soc/core0/core1)                 |
33               +-------------------------------------------------------------+
34
35  As above, there are parent and child devices, child mean each hardware. The child device
36  controls the information of each hardware independent which include clk/power/irq.
37
38  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39  to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42  writing the result to output buffer, disable hardware when core decode done. These two
43  hardwares will decode each frame cyclically.
44
45  For the smi common may not the same for each hardware, can't combine all hardware in one node,
46  or leading to iommu fault when access dram data.
47
48  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
49  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
50  clock when lat start to work, don't have interrupt.
51
52  mt8195: lat soc HW + lat HW + core HW
53  mt8192: lat HW + core HW
54
55properties:
56  compatible:
57    enum:
58      - mediatek,mt8192-vcodec-dec
59      - mediatek,mt8186-vcodec-dec
60      - mediatek,mt8188-vcodec-dec
61      - mediatek,mt8195-vcodec-dec
62
63  reg:
64    maxItems: 1
65
66  iommus:
67    minItems: 1
68    maxItems: 32
69    description: |
70      List of the hardware port in respective IOMMU block for current Socs.
71      Refer to bindings/iommu/mediatek,iommu.yaml.
72
73  mediatek,scp:
74    $ref: /schemas/types.yaml#/definitions/phandle
75    description: |
76      The node of system control processor (SCP), using
77      the remoteproc & rpmsg framework.
78
79  dma-ranges:
80    maxItems: 1
81    description: |
82      Describes the physical address space of IOMMU maps to memory.
83
84  "#address-cells":
85    const: 2
86
87  "#size-cells":
88    const: 2
89
90  ranges: true
91
92# Required child node:
93patternProperties:
94  '^vcodec-lat@[0-9a-f]+$':
95    type: object
96
97    properties:
98      compatible:
99        enum:
100          - mediatek,mtk-vcodec-lat
101          - mediatek,mtk-vcodec-lat-soc
102
103      reg:
104        maxItems: 1
105
106      interrupts:
107        maxItems: 1
108
109      iommus:
110        minItems: 1
111        maxItems: 32
112        description: |
113          List of the hardware port in respective IOMMU block for current Socs.
114          Refer to bindings/iommu/mediatek,iommu.yaml.
115
116      clocks:
117        maxItems: 5
118
119      clock-names:
120        items:
121          - const: sel
122          - const: soc-vdec
123          - const: soc-lat
124          - const: vdec
125          - const: top
126
127      assigned-clocks:
128        maxItems: 1
129
130      assigned-clock-parents:
131        maxItems: 1
132
133      power-domains:
134        maxItems: 1
135
136    required:
137      - compatible
138      - reg
139      - iommus
140      - clocks
141      - clock-names
142      - assigned-clocks
143      - assigned-clock-parents
144      - power-domains
145
146    additionalProperties: false
147
148  '^vcodec-core@[0-9a-f]+$':
149    type: object
150
151    properties:
152      compatible:
153        const: mediatek,mtk-vcodec-core
154
155      reg:
156        maxItems: 1
157
158      interrupts:
159        maxItems: 1
160
161      iommus:
162        minItems: 1
163        maxItems: 32
164        description: |
165          List of the hardware port in respective IOMMU block for current Socs.
166          Refer to bindings/iommu/mediatek,iommu.yaml.
167
168      clocks:
169        maxItems: 5
170
171      clock-names:
172        items:
173          - const: sel
174          - const: soc-vdec
175          - const: soc-lat
176          - const: vdec
177          - const: top
178
179      assigned-clocks:
180        maxItems: 1
181
182      assigned-clock-parents:
183        maxItems: 1
184
185      power-domains:
186        maxItems: 1
187
188    required:
189      - compatible
190      - reg
191      - interrupts
192      - iommus
193      - clocks
194      - clock-names
195      - assigned-clocks
196      - assigned-clock-parents
197      - power-domains
198
199    additionalProperties: false
200
201required:
202  - compatible
203  - reg
204  - iommus
205  - mediatek,scp
206  - dma-ranges
207  - ranges
208
209if:
210  properties:
211    compatible:
212      contains:
213        enum:
214          - mediatek,mtk-vcodec-lat
215
216then:
217  required:
218    - interrupts
219
220additionalProperties: false
221
222examples:
223  - |
224    #include <dt-bindings/interrupt-controller/arm-gic.h>
225    #include <dt-bindings/memory/mt8192-larb-port.h>
226    #include <dt-bindings/interrupt-controller/irq.h>
227    #include <dt-bindings/clock/mt8192-clk.h>
228    #include <dt-bindings/power/mt8192-power.h>
229
230    bus@16000000 {
231        #address-cells = <2>;
232        #size-cells = <2>;
233        ranges = <0 0x16000000 0x16000000 0 0x40000>;
234
235        video-codec@16000000 {
236            compatible = "mediatek,mt8192-vcodec-dec";
237            mediatek,scp = <&scp>;
238            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
239            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
240            #address-cells = <2>;
241            #size-cells = <2>;
242            ranges = <0 0 0 0x16000000 0 0x40000>;
243            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
244            vcodec-lat@10000 {
245                compatible = "mediatek,mtk-vcodec-lat";
246                reg = <0 0x10000 0 0x800>;
247                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
248                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
249                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
250                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
251                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
252                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
253                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
254                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
255                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
256                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
257                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
258                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
259                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
260                    <&topckgen CLK_TOP_MAINPLL_D4>;
261                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
262                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
263                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
264                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
265            };
266
267            vcodec-core@25000 {
268                compatible = "mediatek,mtk-vcodec-core";
269                reg = <0 0x25000 0 0x1000>;
270                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
271                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
272                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
273                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
274                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
275                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
276                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
277                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
278                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
279                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
280                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
281                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
282                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
283                    <&vdecsys CLK_VDEC_VDEC>,
284                    <&vdecsys CLK_VDEC_LAT>,
285                    <&vdecsys CLK_VDEC_LARB1>,
286                    <&topckgen CLK_TOP_MAINPLL_D4>;
287                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
288                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
289                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
290                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
291            };
292        };
293    };
294