1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Encode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Encode is the video encode hardware present in Mediatek
15  SoCs which supports high resolution encoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-enc-vp8
21      - mediatek,mt8173-vcodec-enc
22      - mediatek,mt8183-vcodec-enc
23      - mediatek,mt8188-vcodec-enc
24      - mediatek,mt8192-vcodec-enc
25      - mediatek,mt8195-vcodec-enc
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    minItems: 1
35    maxItems: 5
36
37  clock-names:
38    minItems: 1
39    maxItems: 5
40
41  assigned-clocks: true
42
43  assigned-clock-parents: true
44
45  iommus:
46    minItems: 1
47    maxItems: 32
48    description: |
49      List of the hardware port in respective IOMMU block for current Socs.
50      Refer to bindings/iommu/mediatek,iommu.yaml.
51
52  dma-ranges:
53    maxItems: 1
54    description: |
55      Describes the physical address space of IOMMU maps to memory.
56
57  mediatek,vpu:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      Describes point to vpu.
61
62  mediatek,scp:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    description:
65      Describes point to scp.
66
67  power-domains:
68    maxItems: 1
69
70  "#address-cells":
71    const: 2
72
73  "#size-cells":
74    const: 2
75
76required:
77  - compatible
78  - reg
79  - interrupts
80  - clocks
81  - clock-names
82  - iommus
83  - assigned-clocks
84  - assigned-clock-parents
85
86allOf:
87  - if:
88      properties:
89        compatible:
90          contains:
91            enum:
92              - mediatek,mt8183-vcodec-enc
93              - mediatek,mt8188-vcodec-enc
94              - mediatek,mt8192-vcodec-enc
95              - mediatek,mt8195-vcodec-enc
96
97    then:
98      required:
99        - mediatek,scp
100
101  - if:
102      properties:
103        compatible:
104          contains:
105            enum:
106              - mediatek,mt8173-vcodec-enc-vp8
107              - mediatek,mt8173-vcodec-enc
108
109    then:
110      required:
111        - mediatek,vpu
112
113  - if:
114      properties:
115        compatible:
116          enum:
117            - mediatek,mt8173-vcodec-enc
118            - mediatek,mt8188-vcodec-enc
119            - mediatek,mt8192-vcodec-enc
120            - mediatek,mt8195-vcodec-enc
121
122    then:
123      properties:
124        clock:
125          items:
126            minItems: 1
127            maxItems: 1
128        clock-names:
129          items:
130            - const: venc_sel
131    else:  # for vp8 hw encoder
132      properties:
133        clock:
134          items:
135            minItems: 1
136            maxItems: 1
137        clock-names:
138          items:
139            - const: venc_lt_sel
140
141additionalProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146    #include <dt-bindings/clock/mt8173-clk.h>
147    #include <dt-bindings/memory/mt8173-larb-port.h>
148    #include <dt-bindings/interrupt-controller/irq.h>
149
150    vcodec_enc_avc: vcodec@18002000 {
151      compatible = "mediatek,mt8173-vcodec-enc";
152      reg = <0x18002000 0x1000>;
153      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
154      iommus = <&iommu M4U_PORT_VENC_RCPU>,
155             <&iommu M4U_PORT_VENC_REC>,
156             <&iommu M4U_PORT_VENC_BSDMA>,
157             <&iommu M4U_PORT_VENC_SV_COMV>,
158             <&iommu M4U_PORT_VENC_RD_COMV>,
159             <&iommu M4U_PORT_VENC_CUR_LUMA>,
160             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
161             <&iommu M4U_PORT_VENC_REF_LUMA>,
162             <&iommu M4U_PORT_VENC_REF_CHROMA>,
163             <&iommu M4U_PORT_VENC_NBM_RDMA>,
164             <&iommu M4U_PORT_VENC_NBM_WDMA>;
165      mediatek,vpu = <&vpu>;
166      clocks = <&topckgen CLK_TOP_VENC_SEL>;
167      clock-names = "venc_sel";
168      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
169      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
170    };
171
172    vcodec_enc_vp8: vcodec@19002000 {
173      compatible = "mediatek,mt8173-vcodec-enc-vp8";
174      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
175      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
176      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
177             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
178             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
179             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
180             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
181             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
182             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
183             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
184             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
185      mediatek,vpu = <&vpu>;
186      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
187      clock-names = "venc_lt_sel";
188      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
189      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
190    };
191