1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Decode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-dec
21      - mediatek,mt8183-vcodec-dec
22
23  reg:
24    maxItems: 12
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 8
31
32  clock-names:
33    items:
34      - const: vcodecpll
35      - const: univpll_d2
36      - const: clk_cci400_sel
37      - const: vdec_sel
38      - const: vdecpll
39      - const: vencpll
40      - const: venc_lt_sel
41      - const: vdec_bus_clk_src
42
43  assigned-clocks: true
44
45  assigned-clock-parents: true
46
47  assigned-clock-rates: true
48
49  power-domains:
50    maxItems: 1
51
52  iommus:
53    minItems: 1
54    maxItems: 32
55    description: |
56      List of the hardware port in respective IOMMU block for current Socs.
57      Refer to bindings/iommu/mediatek,iommu.yaml.
58
59  dma-ranges:
60    maxItems: 1
61    description: |
62      Describes the physical address space of IOMMU maps to memory.
63
64  mediatek,larb:
65    $ref: /schemas/types.yaml#/definitions/phandle
66    maxItems: 1
67    description: |
68      Must contain the local arbiters in the current Socs.
69
70  mediatek,vpu:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    maxItems: 1
73    description:
74      Describes point to vpu.
75
76  mediatek,scp:
77    $ref: /schemas/types.yaml#/definitions/phandle
78    maxItems: 1
79    description:
80      Describes point to scp.
81
82required:
83  - compatible
84  - reg
85  - interrupts
86  - clocks
87  - clock-names
88  - iommus
89  - assigned-clocks
90  - assigned-clock-parents
91
92allOf:
93  - if:
94      properties:
95        compatible:
96          contains:
97            enum:
98              - mediatek,mt8183-vcodec-dec
99
100    then:
101      required:
102        - mediatek,scp
103
104  - if:
105      properties:
106        compatible:
107          contains:
108            enum:
109              - mediatek,mt8173-vcodec-dec
110
111    then:
112      required:
113        - mediatek,vpu
114
115additionalProperties: false
116
117examples:
118  - |
119    #include <dt-bindings/interrupt-controller/arm-gic.h>
120    #include <dt-bindings/clock/mt8173-clk.h>
121    #include <dt-bindings/memory/mt8173-larb-port.h>
122    #include <dt-bindings/interrupt-controller/irq.h>
123    #include <dt-bindings/power/mt8173-power.h>
124
125    vcodec_dec: vcodec@16000000 {
126      compatible = "mediatek,mt8173-vcodec-dec";
127      reg = <0x16000000 0x100>,   /*VDEC_SYS*/
128          <0x16020000 0x1000>,  /*VDEC_MISC*/
129          <0x16021000 0x800>,   /*VDEC_LD*/
130          <0x16021800 0x800>,   /*VDEC_TOP*/
131          <0x16022000 0x1000>,  /*VDEC_CM*/
132          <0x16023000 0x1000>,  /*VDEC_AD*/
133          <0x16024000 0x1000>,  /*VDEC_AV*/
134          <0x16025000 0x1000>,  /*VDEC_PP*/
135          <0x16026800 0x800>,   /*VP8_VD*/
136          <0x16027000 0x800>,   /*VP6_VD*/
137          <0x16027800 0x800>,   /*VP8_VL*/
138          <0x16028400 0x400>;   /*VP9_VD*/
139      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
140      mediatek,larb = <&larb1>;
141      iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
142             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
143             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
144             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
145             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
146             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
147             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
148             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
149      mediatek,vpu = <&vpu>;
150      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
151      clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
152             <&topckgen CLK_TOP_UNIVPLL_D2>,
153             <&topckgen CLK_TOP_CCI400_SEL>,
154             <&topckgen CLK_TOP_VDEC_SEL>,
155             <&topckgen CLK_TOP_VCODECPLL>,
156             <&apmixedsys CLK_APMIXED_VENCPLL>,
157             <&topckgen CLK_TOP_VENC_LT_SEL>,
158             <&topckgen CLK_TOP_VCODECPLL_370P5>;
159      clock-names = "vcodecpll",
160                  "univpll_d2",
161                  "clk_cci400_sel",
162                  "vdec_sel",
163                  "vdecpll",
164                  "vencpll",
165                  "venc_lt_sel",
166                  "vdec_bus_clk_src";
167      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
168                      <&topckgen CLK_TOP_CCI400_SEL>,
169                      <&topckgen CLK_TOP_VDEC_SEL>,
170                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
171                      <&apmixedsys CLK_APMIXED_VENCPLL>;
172      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
173                             <&topckgen CLK_TOP_UNIVPLL_D2>,
174                             <&topckgen CLK_TOP_VCODECPLL>;
175      assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
176    };
177