1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Mediatek Video Decode Accelerator
9
10maintainers:
11  - Yunfei Dong <yunfei.dong@mediatek.com>
12
13description: |+
14  Mediatek Video Decode is the video decode hardware present in Mediatek
15  SoCs which supports high resolution decoding functionalities.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt8173-vcodec-dec
21      - mediatek,mt8183-vcodec-dec
22
23  reg:
24    maxItems: 12
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    minItems: 1
31    maxItems: 8
32
33  clock-names:
34    minItems: 1
35    maxItems: 8
36
37  assigned-clocks: true
38
39  assigned-clock-parents: true
40
41  assigned-clock-rates: true
42
43  power-domains:
44    maxItems: 1
45
46  iommus:
47    minItems: 1
48    maxItems: 32
49    description: |
50      List of the hardware port in respective IOMMU block for current Socs.
51      Refer to bindings/iommu/mediatek,iommu.yaml.
52
53  mediatek,vpu:
54    $ref: /schemas/types.yaml#/definitions/phandle
55    description:
56      Describes point to vpu.
57
58  mediatek,scp:
59    $ref: /schemas/types.yaml#/definitions/phandle
60    description:
61      Describes point to scp.
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - iommus
70
71allOf:
72  - if:
73      properties:
74        compatible:
75          contains:
76            enum:
77              - mediatek,mt8183-vcodec-dec
78
79    then:
80      required:
81        - mediatek,scp
82
83      properties:
84        clocks:
85          minItems: 1
86          maxItems: 1
87
88        clock-names:
89          items:
90            - const: vdec
91
92  - if:
93      properties:
94        compatible:
95          contains:
96            enum:
97              - mediatek,mt8173-vcodec-dec
98
99    then:
100      required:
101        - mediatek,vpu
102
103      properties:
104        clocks:
105          minItems: 8
106          maxItems: 8
107
108        clock-names:
109          items:
110            - const: vcodecpll
111            - const: univpll_d2
112            - const: clk_cci400_sel
113            - const: vdec_sel
114            - const: vdecpll
115            - const: vencpll
116            - const: venc_lt_sel
117            - const: vdec_bus_clk_src
118
119additionalProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124    #include <dt-bindings/clock/mt8173-clk.h>
125    #include <dt-bindings/memory/mt8173-larb-port.h>
126    #include <dt-bindings/interrupt-controller/irq.h>
127    #include <dt-bindings/power/mt8173-power.h>
128
129    vcodec_dec: vcodec@16000000 {
130      compatible = "mediatek,mt8173-vcodec-dec";
131      reg = <0x16000000 0x100>,   /*VDEC_SYS*/
132          <0x16020000 0x1000>,  /*VDEC_MISC*/
133          <0x16021000 0x800>,   /*VDEC_LD*/
134          <0x16021800 0x800>,   /*VDEC_TOP*/
135          <0x16022000 0x1000>,  /*VDEC_CM*/
136          <0x16023000 0x1000>,  /*VDEC_AD*/
137          <0x16024000 0x1000>,  /*VDEC_AV*/
138          <0x16025000 0x1000>,  /*VDEC_PP*/
139          <0x16026800 0x800>,   /*VP8_VD*/
140          <0x16027000 0x800>,   /*VP6_VD*/
141          <0x16027800 0x800>,   /*VP8_VL*/
142          <0x16028400 0x400>;   /*VP9_VD*/
143      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
144      iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
145             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
146             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
147             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
148             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
149             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
150             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
151             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
152      mediatek,vpu = <&vpu>;
153      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
154      clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
155             <&topckgen CLK_TOP_UNIVPLL_D2>,
156             <&topckgen CLK_TOP_CCI400_SEL>,
157             <&topckgen CLK_TOP_VDEC_SEL>,
158             <&topckgen CLK_TOP_VCODECPLL>,
159             <&apmixedsys CLK_APMIXED_VENCPLL>,
160             <&topckgen CLK_TOP_VENC_LT_SEL>,
161             <&topckgen CLK_TOP_VCODECPLL_370P5>;
162      clock-names = "vcodecpll",
163                  "univpll_d2",
164                  "clk_cci400_sel",
165                  "vdec_sel",
166                  "vdecpll",
167                  "vencpll",
168                  "venc_lt_sel",
169                  "vdec_bus_clk_src";
170      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
171                      <&topckgen CLK_TOP_CCI400_SEL>,
172                      <&topckgen CLK_TOP_VDEC_SEL>,
173                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
174                      <&apmixedsys CLK_APMIXED_VENCPLL>;
175      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
176                             <&topckgen CLK_TOP_UNIVPLL_D2>,
177                             <&topckgen CLK_TOP_VCODECPLL>;
178      assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
179    };
180