1*4ad7b396SMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4ad7b396SMoudy Ho%YAML 1.2
3*4ad7b396SMoudy Ho---
4*4ad7b396SMoudy Ho$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5*4ad7b396SMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4ad7b396SMoudy Ho
7*4ad7b396SMoudy Hotitle: MediaTek Resizer
8*4ad7b396SMoudy Ho
9*4ad7b396SMoudy Homaintainers:
10*4ad7b396SMoudy Ho  - Matthias Brugger <matthias.bgg@gmail.com>
11*4ad7b396SMoudy Ho  - Moudy Ho <moudy.ho@mediatek.com>
12*4ad7b396SMoudy Ho
13*4ad7b396SMoudy Hodescription: |
14*4ad7b396SMoudy Ho  One of Media Data Path 3 (MDP3) components used to do frame resizing.
15*4ad7b396SMoudy Ho
16*4ad7b396SMoudy Hoproperties:
17*4ad7b396SMoudy Ho  compatible:
18*4ad7b396SMoudy Ho    items:
19*4ad7b396SMoudy Ho      - enum:
20*4ad7b396SMoudy Ho          - mediatek,mt8183-mdp3-rsz
21*4ad7b396SMoudy Ho
22*4ad7b396SMoudy Ho  reg:
23*4ad7b396SMoudy Ho    maxItems: 1
24*4ad7b396SMoudy Ho
25*4ad7b396SMoudy Ho  mediatek,gce-client-reg:
26*4ad7b396SMoudy Ho    $ref: /schemas/types.yaml#/definitions/phandle-array
27*4ad7b396SMoudy Ho    items:
28*4ad7b396SMoudy Ho      items:
29*4ad7b396SMoudy Ho        - description: phandle of GCE
30*4ad7b396SMoudy Ho        - description: GCE subsys id
31*4ad7b396SMoudy Ho        - description: register offset
32*4ad7b396SMoudy Ho        - description: register size
33*4ad7b396SMoudy Ho    description: The register of client driver can be configured by gce with
34*4ad7b396SMoudy Ho      4 arguments defined in this property. Each GCE subsys id is mapping to
35*4ad7b396SMoudy Ho      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36*4ad7b396SMoudy Ho
37*4ad7b396SMoudy Ho  mediatek,gce-events:
38*4ad7b396SMoudy Ho    description:
39*4ad7b396SMoudy Ho      The event id which is mapping to the specific hardware event signal
40*4ad7b396SMoudy Ho      to gce. The event id is defined in the gce header
41*4ad7b396SMoudy Ho      include/dt-bindings/gce/<chip>-gce.h of each chips.
42*4ad7b396SMoudy Ho    $ref: /schemas/types.yaml#/definitions/uint32-array
43*4ad7b396SMoudy Ho
44*4ad7b396SMoudy Ho  clocks:
45*4ad7b396SMoudy Ho    minItems: 1
46*4ad7b396SMoudy Ho
47*4ad7b396SMoudy Horequired:
48*4ad7b396SMoudy Ho  - compatible
49*4ad7b396SMoudy Ho  - reg
50*4ad7b396SMoudy Ho  - mediatek,gce-client-reg
51*4ad7b396SMoudy Ho  - mediatek,gce-events
52*4ad7b396SMoudy Ho  - clocks
53*4ad7b396SMoudy Ho
54*4ad7b396SMoudy HoadditionalProperties: false
55*4ad7b396SMoudy Ho
56*4ad7b396SMoudy Hoexamples:
57*4ad7b396SMoudy Ho  - |
58*4ad7b396SMoudy Ho    #include <dt-bindings/clock/mt8183-clk.h>
59*4ad7b396SMoudy Ho    #include <dt-bindings/gce/mt8183-gce.h>
60*4ad7b396SMoudy Ho
61*4ad7b396SMoudy Ho    mdp3_rsz0: mdp3-rsz0@14003000 {
62*4ad7b396SMoudy Ho      compatible = "mediatek,mt8183-mdp3-rsz";
63*4ad7b396SMoudy Ho      reg = <0x14003000 0x1000>;
64*4ad7b396SMoudy Ho      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
65*4ad7b396SMoudy Ho      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
66*4ad7b396SMoudy Ho                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
67*4ad7b396SMoudy Ho      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
68*4ad7b396SMoudy Ho    };
69*4ad7b396SMoudy Ho
70*4ad7b396SMoudy Ho    mdp3_rsz1: mdp3-rsz1@14004000 {
71*4ad7b396SMoudy Ho      compatible = "mediatek,mt8183-mdp3-rsz";
72*4ad7b396SMoudy Ho      reg = <0x14004000 0x1000>;
73*4ad7b396SMoudy Ho      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
74*4ad7b396SMoudy Ho      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
75*4ad7b396SMoudy Ho                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
76*4ad7b396SMoudy Ho      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
77*4ad7b396SMoudy Ho    };
78