138ad8b32SMing Qian# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
238ad8b32SMing Qian
338ad8b32SMing Qian%YAML 1.2
438ad8b32SMing Qian---
538ad8b32SMing Qian$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
638ad8b32SMing Qian$schema: http://devicetree.org/meta-schemas/core.yaml#
738ad8b32SMing Qian
838ad8b32SMing Qiantitle: Amphion VPU codec IP
938ad8b32SMing Qian
1038ad8b32SMing Qianmaintainers:
1138ad8b32SMing Qian  - Ming Qian <ming.qian@nxp.com>
1238ad8b32SMing Qian  - Shijie Qin <shijie.qin@nxp.com>
1338ad8b32SMing Qian
1438ad8b32SMing Qiandescription: |-
1538ad8b32SMing Qian  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
1638ad8b32SMing Qian  on NXP i.MX8Q SoCs.
1738ad8b32SMing Qian
1838ad8b32SMing Qianproperties:
1938ad8b32SMing Qian  $nodename:
2038ad8b32SMing Qian    pattern: "^vpu@[0-9a-f]+$"
2138ad8b32SMing Qian
2238ad8b32SMing Qian  compatible:
2338ad8b32SMing Qian    items:
2438ad8b32SMing Qian      - enum:
2538ad8b32SMing Qian          - nxp,imx8qm-vpu
2638ad8b32SMing Qian          - nxp,imx8qxp-vpu
2738ad8b32SMing Qian
2838ad8b32SMing Qian  reg:
2938ad8b32SMing Qian    maxItems: 1
3038ad8b32SMing Qian
3138ad8b32SMing Qian  power-domains:
3238ad8b32SMing Qian    maxItems: 1
3338ad8b32SMing Qian
3438ad8b32SMing Qian  "#address-cells":
3538ad8b32SMing Qian    const: 1
3638ad8b32SMing Qian
3738ad8b32SMing Qian  "#size-cells":
3838ad8b32SMing Qian    const: 1
3938ad8b32SMing Qian
4038ad8b32SMing Qian  ranges: true
4138ad8b32SMing Qian
4238ad8b32SMing QianpatternProperties:
4338ad8b32SMing Qian  "^mailbox@[0-9a-f]+$":
4438ad8b32SMing Qian    description:
4538ad8b32SMing Qian      Each vpu encoder or decoder correspond a MU, which used for communication
4638ad8b32SMing Qian      between driver and firmware. Implement via mailbox on driver.
4738ad8b32SMing Qian    $ref: ../mailbox/fsl,mu.yaml#
4838ad8b32SMing Qian
4938ad8b32SMing Qian
50*9578de86SPeng Fan  "^vpu-core@[0-9a-f]+$":
5138ad8b32SMing Qian    description:
5238ad8b32SMing Qian      Each core correspond a decoder or encoder, need to configure them
5338ad8b32SMing Qian      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
5438ad8b32SMing Qian      has one decoder and one encoder.
5538ad8b32SMing Qian    type: object
5638ad8b32SMing Qian
5738ad8b32SMing Qian    properties:
5838ad8b32SMing Qian      compatible:
5938ad8b32SMing Qian        items:
6038ad8b32SMing Qian          - enum:
6138ad8b32SMing Qian              - nxp,imx8q-vpu-decoder
6238ad8b32SMing Qian              - nxp,imx8q-vpu-encoder
6338ad8b32SMing Qian
6438ad8b32SMing Qian      reg:
6538ad8b32SMing Qian        maxItems: 1
6638ad8b32SMing Qian
6738ad8b32SMing Qian      power-domains:
6838ad8b32SMing Qian        maxItems: 1
6938ad8b32SMing Qian
7038ad8b32SMing Qian      mbox-names:
7138ad8b32SMing Qian        items:
7238ad8b32SMing Qian          - const: tx0
7338ad8b32SMing Qian          - const: tx1
7438ad8b32SMing Qian          - const: rx
7538ad8b32SMing Qian
7638ad8b32SMing Qian      mboxes:
7738ad8b32SMing Qian        description:
7838ad8b32SMing Qian          List of phandle of 2 MU channels for tx, 1 MU channel for rx.
7938ad8b32SMing Qian        maxItems: 3
8038ad8b32SMing Qian
8138ad8b32SMing Qian      memory-region:
8238ad8b32SMing Qian        description:
8338ad8b32SMing Qian          Phandle to the reserved memory nodes to be associated with the
8438ad8b32SMing Qian          remoteproc device. The reserved memory nodes should be carveout nodes,
8538ad8b32SMing Qian          and should be defined as per the bindings in
8638ad8b32SMing Qian          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
8738ad8b32SMing Qian        items:
8838ad8b32SMing Qian          - description: region reserved for firmware image sections.
8938ad8b32SMing Qian          - description: region used for RPC shared memory between firmware and
9038ad8b32SMing Qian                         driver.
9138ad8b32SMing Qian
9238ad8b32SMing Qian    required:
9338ad8b32SMing Qian      - compatible
9438ad8b32SMing Qian      - reg
9538ad8b32SMing Qian      - power-domains
9638ad8b32SMing Qian      - mbox-names
9738ad8b32SMing Qian      - mboxes
9838ad8b32SMing Qian      - memory-region
9938ad8b32SMing Qian
10038ad8b32SMing Qian    additionalProperties: false
10138ad8b32SMing Qian
10238ad8b32SMing Qianrequired:
10338ad8b32SMing Qian  - compatible
10438ad8b32SMing Qian  - reg
10538ad8b32SMing Qian  - power-domains
10638ad8b32SMing Qian
10738ad8b32SMing QianadditionalProperties: false
10838ad8b32SMing Qian
10938ad8b32SMing Qianexamples:
11038ad8b32SMing Qian  # Device node example for i.MX8QM platform:
11138ad8b32SMing Qian  - |
11238ad8b32SMing Qian    #include <dt-bindings/firmware/imx/rsrc.h>
11338ad8b32SMing Qian
11438ad8b32SMing Qian    vpu: vpu@2c000000 {
11538ad8b32SMing Qian      compatible = "nxp,imx8qm-vpu";
11638ad8b32SMing Qian      ranges = <0x2c000000 0x2c000000 0x2000000>;
11738ad8b32SMing Qian      reg = <0x2c000000 0x1000000>;
11838ad8b32SMing Qian      #address-cells = <1>;
11938ad8b32SMing Qian      #size-cells = <1>;
12038ad8b32SMing Qian      power-domains = <&pd IMX_SC_R_VPU>;
12138ad8b32SMing Qian
12238ad8b32SMing Qian      mu_m0: mailbox@2d000000 {
12338ad8b32SMing Qian        compatible = "fsl,imx6sx-mu";
12438ad8b32SMing Qian        reg = <0x2d000000 0x20000>;
12538ad8b32SMing Qian        interrupts = <0 472 4>;
12638ad8b32SMing Qian        #mbox-cells = <2>;
12738ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_MU_0>;
12838ad8b32SMing Qian      };
12938ad8b32SMing Qian
13038ad8b32SMing Qian      mu1_m0: mailbox@2d020000 {
13138ad8b32SMing Qian        compatible = "fsl,imx6sx-mu";
13238ad8b32SMing Qian        reg = <0x2d020000 0x20000>;
13338ad8b32SMing Qian        interrupts = <0 473 4>;
13438ad8b32SMing Qian        #mbox-cells = <2>;
13538ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_MU_1>;
13638ad8b32SMing Qian      };
13738ad8b32SMing Qian
13838ad8b32SMing Qian      mu2_m0: mailbox@2d040000 {
13938ad8b32SMing Qian        compatible = "fsl,imx6sx-mu";
14038ad8b32SMing Qian        reg = <0x2d040000 0x20000>;
14138ad8b32SMing Qian        interrupts = <0 474 4>;
14238ad8b32SMing Qian        #mbox-cells = <2>;
14338ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_MU_2>;
14438ad8b32SMing Qian      };
14538ad8b32SMing Qian
146*9578de86SPeng Fan      vpu_core0: vpu-core@2d080000 {
14738ad8b32SMing Qian        compatible = "nxp,imx8q-vpu-decoder";
14838ad8b32SMing Qian        reg = <0x2d080000 0x10000>;
14938ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
15038ad8b32SMing Qian        mbox-names = "tx0", "tx1", "rx";
15138ad8b32SMing Qian        mboxes = <&mu_m0 0 0>,
15238ad8b32SMing Qian                 <&mu_m0 0 1>,
15338ad8b32SMing Qian                 <&mu_m0 1 0>;
15438ad8b32SMing Qian        memory-region = <&decoder_boot>, <&decoder_rpc>;
15538ad8b32SMing Qian      };
15638ad8b32SMing Qian
157*9578de86SPeng Fan      vpu_core1: vpu-core@2d090000 {
15838ad8b32SMing Qian        compatible = "nxp,imx8q-vpu-encoder";
15938ad8b32SMing Qian        reg = <0x2d090000 0x10000>;
16038ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
16138ad8b32SMing Qian        mbox-names = "tx0", "tx1", "rx";
16238ad8b32SMing Qian        mboxes = <&mu1_m0 0 0>,
16338ad8b32SMing Qian                 <&mu1_m0 0 1>,
16438ad8b32SMing Qian                 <&mu1_m0 1 0>;
16538ad8b32SMing Qian        memory-region = <&encoder1_boot>, <&encoder1_rpc>;
16638ad8b32SMing Qian      };
16738ad8b32SMing Qian
168*9578de86SPeng Fan      vpu_core2: vpu-core@2d0a0000 {
16938ad8b32SMing Qian        reg = <0x2d0a0000 0x10000>;
17038ad8b32SMing Qian        compatible = "nxp,imx8q-vpu-encoder";
17138ad8b32SMing Qian        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
17238ad8b32SMing Qian        mbox-names = "tx0", "tx1", "rx";
17338ad8b32SMing Qian        mboxes = <&mu2_m0 0 0>,
17438ad8b32SMing Qian                 <&mu2_m0 0 1>,
17538ad8b32SMing Qian                 <&mu2_m0 1 0>;
17638ad8b32SMing Qian        memory-region = <&encoder2_boot>, <&encoder2_rpc>;
17738ad8b32SMing Qian      };
17838ad8b32SMing Qian    };
17938ad8b32SMing Qian
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