1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A31 CMOS Sensor Interface (CSI) Device Tree Bindings
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - allwinner,sun6i-a31-csi
17      - allwinner,sun8i-a83t-csi
18      - allwinner,sun8i-h3-csi
19      - allwinner,sun8i-v3s-csi
20      - allwinner,sun50i-a64-csi
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: Bus Clock
31      - description: Module Clock
32      - description: DRAM Clock
33
34  clock-names:
35    items:
36      - const: bus
37      - const: mod
38      - const: ram
39
40  resets:
41    maxItems: 1
42
43  # See ./video-interfaces.txt for details
44  port:
45    type: object
46
47    properties:
48      endpoint:
49        type: object
50
51        properties:
52          remote-endpoint: true
53
54          bus-width:
55            enum: [ 8, 10, 12, 16 ]
56
57          pclk-sample: true
58          hsync-active: true
59          vsync-active: true
60
61        required:
62          - bus-width
63          - remote-endpoint
64
65    required:
66      - endpoint
67
68    additionalProperties: false
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - clocks
75  - clock-names
76  - resets
77
78additionalProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/interrupt-controller/arm-gic.h>
83    #include <dt-bindings/clock/sun8i-v3s-ccu.h>
84    #include <dt-bindings/reset/sun8i-v3s-ccu.h>
85
86    csi1: csi@1cb4000 {
87        compatible = "allwinner,sun8i-v3s-csi";
88        reg = <0x01cb4000 0x1000>;
89        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
90        clocks = <&ccu CLK_BUS_CSI>,
91                 <&ccu CLK_CSI1_SCLK>,
92                 <&ccu CLK_DRAM_CSI>;
93        clock-names = "bus",
94                      "mod",
95                      "ram";
96        resets = <&ccu RST_BUS_CSI>;
97
98        port {
99            /* Parallel bus endpoint */
100            csi1_ep: endpoint {
101                remote-endpoint = <&adv7611_ep>;
102                bus-width = <16>;
103
104                /*
105                 * If hsync-active/vsync-active are missing,
106                 * embedded BT.656 sync is used.
107                 */
108                 hsync-active = <0>; /* Active low */
109                 vsync-active = <0>; /* Active low */
110                 pclk-sample = <1>;  /* Rising */
111            };
112        };
113    };
114
115...
116