1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner H3 Deinterlace Device Tree Bindings
8
9maintainers:
10  - Jernej Skrabec <jernej.skrabec@siol.net>
11  - Chen-Yu Tsai <wens@csie.org>
12  - Maxime Ripard <mripard@kernel.org>
13
14description: |-
15  The Allwinner H3 and later has a deinterlace core used for
16  deinterlacing interlaced video content.
17
18properties:
19  compatible:
20    const: allwinner,sun8i-h3-deinterlace
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: Deinterlace interface clock
31      - description: Deinterlace module clock
32      - description: Deinterlace DRAM clock
33
34  clock-names:
35    items:
36      - const: bus
37      - const: mod
38      - const: ram
39
40  resets:
41    maxItems: 1
42
43  interconnects:
44    maxItems: 1
45
46  interconnect-names:
47    const: dma-mem
48
49required:
50  - compatible
51  - reg
52  - interrupts
53  - clocks
54
55additionalProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/interrupt-controller/arm-gic.h>
60    #include <dt-bindings/clock/sun8i-h3-ccu.h>
61    #include <dt-bindings/reset/sun8i-h3-ccu.h>
62
63    deinterlace: deinterlace@1400000 {
64        compatible = "allwinner,sun8i-h3-deinterlace";
65        reg = <0x01400000 0x20000>;
66        clocks = <&ccu CLK_BUS_DEINTERLACE>,
67                 <&ccu CLK_DEINTERLACE>,
68                 <&ccu CLK_DRAM_DEINTERLACE>;
69        clock-names = "bus", "mod", "ram";
70        resets = <&ccu RST_BUS_DEINTERLACE>;
71        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72        interconnects = <&mbus 9>;
73        interconnect-names = "dma-mem";
74    };
75
76...
77