1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: STMicroelectronics STM32 IPC controller bindings
8
9description:
10  The IPCC block provides a non blocking signaling mechanism to post and
11  retrieve messages in an atomic way between two processors.
12  It provides the signaling for N bidirectionnal channels. The number of
13  channels (N) can be read from a dedicated register.
14
15maintainers:
16  - Fabien Dessenne <fabien.dessenne@st.com>
17  - Arnaud Pouliquen <arnaud.pouliquen@st.com>
18
19properties:
20  compatible:
21    const: st,stm32mp1-ipcc
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    maxItems: 1
28
29  interrupts:
30    items:
31      - description: rx channel occupied
32      - description: tx channel free
33      - description: wakeup source
34    minItems: 2
35    maxItems: 3
36
37  interrupt-names:
38    items:
39      - const: rx
40      - const: tx
41      - const: wakeup
42    minItems: 2
43    maxItems: 3
44
45  wakeup-source: true
46
47  "#mbox-cells":
48    const: 1
49
50  st,proc-id:
51    description: Processor id using the mailbox (0 or 1)
52    $ref: /schemas/types.yaml#/definitions/uint32
53    enum: [0, 1]
54
55required:
56  - compatible
57  - reg
58  - st,proc-id
59  - clocks
60  - interrupt-names
61  - "#mbox-cells"
62  - interrupts
63
64additionalProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/interrupt-controller/arm-gic.h>
69    #include <dt-bindings/clock/stm32mp1-clks.h>
70    ipcc: mailbox@4c001000 {
71      compatible = "st,stm32mp1-ipcc";
72      #mbox-cells = <1>;
73      reg = <0x4c001000 0x400>;
74      st,proc-id = <0>;
75      interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
76      		      <&intc GIC_SPI 101 IRQ_TYPE_NONE>,
77      		      <&aiec 62 1>;
78      interrupt-names = "rx", "tx", "wakeup";
79      clocks = <&rcc_clk IPCC>;
80      wakeup-source;
81    };
82
83...
84