xref: /openbmc/linux/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1afa092e1SAllen-KH Cheng# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2afa092e1SAllen-KH Cheng%YAML 1.2
3afa092e1SAllen-KH Cheng---
4afa092e1SAllen-KH Cheng$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5afa092e1SAllen-KH Cheng$schema: http://devicetree.org/meta-schemas/core.yaml#
6afa092e1SAllen-KH Cheng
7afa092e1SAllen-KH Chengtitle: Mediatek ADSP mailbox
8afa092e1SAllen-KH Cheng
9afa092e1SAllen-KH Chengmaintainers:
10afa092e1SAllen-KH Cheng  - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
11afa092e1SAllen-KH Cheng
12afa092e1SAllen-KH Chengdescription: |
13afa092e1SAllen-KH Cheng  The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
14*dea27cdaSTinghan Shen  to communicate with ADSP by passing messages through two mailbox channels.
15afa092e1SAllen-KH Cheng  The MTK ADSP mailbox IPC also provides the ability for one processor to
16afa092e1SAllen-KH Cheng  signal the other processor using interrupts.
17afa092e1SAllen-KH Cheng
18afa092e1SAllen-KH Chengproperties:
19afa092e1SAllen-KH Cheng  compatible:
20*dea27cdaSTinghan Shen    enum:
21*dea27cdaSTinghan Shen      - mediatek,mt8195-adsp-mbox
22*dea27cdaSTinghan Shen      - mediatek,mt8186-adsp-mbox
23afa092e1SAllen-KH Cheng
24afa092e1SAllen-KH Cheng  "#mbox-cells":
25afa092e1SAllen-KH Cheng    const: 0
26afa092e1SAllen-KH Cheng
27afa092e1SAllen-KH Cheng  reg:
28afa092e1SAllen-KH Cheng    maxItems: 1
29afa092e1SAllen-KH Cheng
30afa092e1SAllen-KH Cheng  interrupts:
31afa092e1SAllen-KH Cheng    maxItems: 1
32afa092e1SAllen-KH Cheng
33afa092e1SAllen-KH Chengrequired:
34afa092e1SAllen-KH Cheng  - compatible
35afa092e1SAllen-KH Cheng  - "#mbox-cells"
36afa092e1SAllen-KH Cheng  - reg
37afa092e1SAllen-KH Cheng  - interrupts
38afa092e1SAllen-KH Cheng
39afa092e1SAllen-KH ChengadditionalProperties: false
40afa092e1SAllen-KH Cheng
41afa092e1SAllen-KH Chengexamples:
42afa092e1SAllen-KH Cheng  - |
43afa092e1SAllen-KH Cheng    #include <dt-bindings/interrupt-controller/arm-gic.h>
44afa092e1SAllen-KH Cheng    #include <dt-bindings/interrupt-controller/irq.h>
45afa092e1SAllen-KH Cheng
46afa092e1SAllen-KH Cheng    adsp_mailbox0:mailbox@10816000 {
47afa092e1SAllen-KH Cheng        compatible = "mediatek,mt8195-adsp-mbox";
48afa092e1SAllen-KH Cheng        #mbox-cells = <0>;
49afa092e1SAllen-KH Cheng        reg = <0x10816000 0x1000>;
50afa092e1SAllen-KH Cheng        interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
51afa092e1SAllen-KH Cheng    };
52