1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX Messaging Unit (MU)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description: |
13  The Messaging Unit module enables two processors within the SoC to
14  communicate and coordinate by passing messages (e.g. data, status
15  and control) through the MU interface. The MU also provides the ability
16  for one processor to signal the other processor using interrupts.
17
18  Because the MU manages the messaging between processors, the MU uses
19  different clocks (from each side of the different peripheral buses).
20  Therefore, the MU must synchronize the accesses from one side to the
21  other. The MU accomplishes synchronization using two sets of matching
22  registers (Processor A-facing, Processor B-facing).
23
24properties:
25  compatible:
26    oneOf:
27      - const: fsl,imx6sx-mu
28      - const: fsl,imx7ulp-mu
29      - const: fsl,imx8-mu-scu
30      - items:
31          - enum:
32              - fsl,imx7s-mu
33              - fsl,imx8mq-mu
34              - fsl,imx8mm-mu
35              - fsl,imx8mn-mu
36              - fsl,imx8mp-mu
37              - fsl,imx8qxp-mu
38          - const: fsl,imx6sx-mu
39      - description: To communicate with i.MX8 SCU with fast IPC
40        items:
41          - const: fsl,imx8-mu-scu
42          - const: fsl,imx8qxp-mu
43          - const: fsl,imx6sx-mu
44
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  "#mbox-cells":
52    description: |
53      <&phandle type channel>
54      phandle   : Label name of controller
55      type      : Channel type
56      channel   : Channel number
57
58      This MU support 4 type of unidirectional channels, each type
59      has 4 channels. A total of 16 channels. Following types are
60      supported:
61      0 - TX channel with 32bit transmit register and IRQ transmit
62          acknowledgment support.
63      1 - RX channel with 32bit receive register and IRQ support
64      2 - TX doorbell channel. Without own register and no ACK support.
65      3 - RX doorbell channel.
66    const: 2
67
68  clocks:
69    maxItems: 1
70
71  fsl,mu-side-b:
72    description: boolean, if present, means it is for side B MU.
73    type: boolean
74
75  power-domains:
76    maxItems: 1
77
78required:
79  - compatible
80  - reg
81  - interrupts
82  - "#mbox-cells"
83
84additionalProperties: false
85
86examples:
87  - |
88    #include <dt-bindings/interrupt-controller/arm-gic.h>
89
90    mailbox@5d1b0000 {
91        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
92        reg = <0x5d1b0000 0x10000>;
93        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
94        #mbox-cells = <2>;
95    };
96