1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX Messaging Unit (MU)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description: |
13  The Messaging Unit module enables two processors within the SoC to
14  communicate and coordinate by passing messages (e.g. data, status
15  and control) through the MU interface. The MU also provides the ability
16  for one processor to signal the other processor using interrupts.
17
18  Because the MU manages the messaging between processors, the MU uses
19  different clocks (from each side of the different peripheral buses).
20  Therefore, the MU must synchronize the accesses from one side to the
21  other. The MU accomplishes synchronization using two sets of matching
22  registers (Processor A-facing, Processor B-facing).
23
24properties:
25  compatible:
26    oneOf:
27      - const: fsl,imx6sx-mu
28      - const: fsl,imx7ulp-mu
29      - const: fsl,imx8ulp-mu
30      - const: fsl,imx8-mu-scu
31      - const: fsl,imx8-mu-seco
32      - const: fsl,imx8ulp-mu-s4
33      - items:
34          - enum:
35              - fsl,imx7s-mu
36              - fsl,imx8mq-mu
37              - fsl,imx8mm-mu
38              - fsl,imx8mn-mu
39              - fsl,imx8mp-mu
40              - fsl,imx8qm-mu
41              - fsl,imx8qxp-mu
42          - const: fsl,imx6sx-mu
43      - description: To communicate with i.MX8 SCU with fast IPC
44        items:
45          - const: fsl,imx8-mu-scu
46          - enum:
47              - fsl,imx8qm-mu
48              - fsl,imx8qxp-mu
49          - const: fsl,imx6sx-mu
50
51  reg:
52    maxItems: 1
53
54  interrupts:
55    maxItems: 1
56
57  "#mbox-cells":
58    description: |
59      <&phandle type channel>
60      phandle   : Label name of controller
61      type      : Channel type
62      channel   : Channel number
63
64      This MU support 4 type of unidirectional channels, each type
65      has 4 channels. A total of 16 channels. Following types are
66      supported:
67      0 - TX channel with 32bit transmit register and IRQ transmit
68          acknowledgment support.
69      1 - RX channel with 32bit receive register and IRQ support
70      2 - TX doorbell channel. Without own register and no ACK support.
71      3 - RX doorbell channel.
72    const: 2
73
74  clocks:
75    maxItems: 1
76
77  fsl,mu-side-b:
78    description: boolean, if present, means it is for side B MU.
79    type: boolean
80
81  power-domains:
82    maxItems: 1
83
84required:
85  - compatible
86  - reg
87  - interrupts
88  - "#mbox-cells"
89
90additionalProperties: false
91
92examples:
93  - |
94    #include <dt-bindings/interrupt-controller/arm-gic.h>
95
96    mailbox@5d1b0000 {
97        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
98        reg = <0x5d1b0000 0x10000>;
99        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
100        #mbox-cells = <2>;
101    };
102