1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX Messaging Unit (MU) 8 9maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 12description: | 13 The Messaging Unit module enables two processors within the SoC to 14 communicate and coordinate by passing messages (e.g. data, status 15 and control) through the MU interface. The MU also provides the ability 16 for one processor to signal the other processor using interrupts. 17 18 Because the MU manages the messaging between processors, the MU uses 19 different clocks (from each side of the different peripheral buses). 20 Therefore, the MU must synchronize the accesses from one side to the 21 other. The MU accomplishes synchronization using two sets of matching 22 registers (Processor A-facing, Processor B-facing). 23 24properties: 25 compatible: 26 oneOf: 27 - const: fsl,imx6sx-mu 28 - const: fsl,imx7ulp-mu 29 - const: fsl,imx8ulp-mu 30 - const: fsl,imx8-mu-scu 31 - const: fsl,imx8-mu-seco 32 - const: fsl,imx8ulp-mu-s4 33 - items: 34 - const: fsl,imx93-mu 35 - const: fsl,imx8ulp-mu 36 - items: 37 - enum: 38 - fsl,imx7s-mu 39 - fsl,imx8mq-mu 40 - fsl,imx8mm-mu 41 - fsl,imx8mn-mu 42 - fsl,imx8mp-mu 43 - fsl,imx8qm-mu 44 - fsl,imx8qxp-mu 45 - const: fsl,imx6sx-mu 46 - description: To communicate with i.MX8 SCU with fast IPC 47 items: 48 - const: fsl,imx8-mu-scu 49 - enum: 50 - fsl,imx8qm-mu 51 - fsl,imx8qxp-mu 52 - const: fsl,imx6sx-mu 53 54 reg: 55 maxItems: 1 56 57 interrupts: 58 maxItems: 1 59 60 "#mbox-cells": 61 description: | 62 <&phandle type channel> 63 phandle : Label name of controller 64 type : Channel type 65 channel : Channel number 66 67 This MU support 4 type of unidirectional channels, each type 68 has 4 channels. A total of 16 channels. Following types are 69 supported: 70 0 - TX channel with 32bit transmit register and IRQ transmit 71 acknowledgment support. 72 1 - RX channel with 32bit receive register and IRQ support 73 2 - TX doorbell channel. Without own register and no ACK support. 74 3 - RX doorbell channel. 75 const: 2 76 77 clocks: 78 maxItems: 1 79 80 fsl,mu-side-b: 81 description: boolean, if present, means it is for side B MU. 82 type: boolean 83 84 power-domains: 85 maxItems: 1 86 87required: 88 - compatible 89 - reg 90 - interrupts 91 - "#mbox-cells" 92 93additionalProperties: false 94 95examples: 96 - | 97 #include <dt-bindings/interrupt-controller/arm-gic.h> 98 99 mailbox@5d1b0000 { 100 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 101 reg = <0x5d1b0000 0x10000>; 102 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 103 #mbox-cells = <2>; 104 }; 105