1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip IOMMU
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |+
13  A Rockchip DRM iommu translates io virtual addresses to physical addresses for
14  its master device. Each slave device is bound to a single master device and
15  shares its clocks, power domain and irq.
16
17  For information on assigning IOMMU controller to its peripheral devices,
18  see generic IOMMU bindings.
19
20properties:
21  compatible:
22    enum:
23      - rockchip,iommu
24      - rockchip,rk3568-iommu
25
26  reg:
27    items:
28      - description: configuration registers for MMU instance 0
29      - description: configuration registers for MMU instance 1
30    minItems: 1
31    maxItems: 2
32
33  interrupts:
34    items:
35      - description: interruption for MMU instance 0
36      - description: interruption for MMU instance 1
37    minItems: 1
38    maxItems: 2
39
40  clocks:
41    items:
42      - description: Core clock
43      - description: Interface clock
44
45  clock-names:
46    items:
47      - const: aclk
48      - const: iface
49
50  "#iommu-cells":
51    const: 0
52
53  power-domains:
54    maxItems: 1
55
56  rockchip,disable-mmu-reset:
57    $ref: /schemas/types.yaml#/definitions/flag
58    description: |
59      Do not use the mmu reset operation.
60      Some mmu instances may produce unexpected results
61      when the reset operation is used.
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - "#iommu-cells"
70
71additionalProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/clock/rk3399-cru.h>
76    #include <dt-bindings/interrupt-controller/arm-gic.h>
77
78    vopl_mmu: iommu@ff940300 {
79      compatible = "rockchip,iommu";
80      reg = <0xff940300 0x100>;
81      interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
82      clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
83      clock-names = "aclk", "iface";
84      #iommu-cells = <0>;
85    };
86