1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas VMSA-Compatible IOMMU
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12description:
13  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
14  It provides address translation for bus masters outside of the CPU, each
15  connected to the IPMMU through a port called micro-TLB.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
23              - renesas,ipmmu-r8a7742  # RZ/G1H
24              - renesas,ipmmu-r8a7743  # RZ/G1M
25              - renesas,ipmmu-r8a7744  # RZ/G1N
26              - renesas,ipmmu-r8a7745  # RZ/G1E
27              - renesas,ipmmu-r8a7790  # R-Car H2
28              - renesas,ipmmu-r8a7791  # R-Car M2-W
29              - renesas,ipmmu-r8a7793  # R-Car M2-N
30              - renesas,ipmmu-r8a7794  # R-Car E2
31          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
32      - items:
33          - enum:
34              - renesas,ipmmu-r8a774a1 # RZ/G2M
35              - renesas,ipmmu-r8a774b1 # RZ/G2N
36              - renesas,ipmmu-r8a774c0 # RZ/G2E
37              - renesas,ipmmu-r8a774e1 # RZ/G2H
38              - renesas,ipmmu-r8a7795  # R-Car H3
39              - renesas,ipmmu-r8a7796  # R-Car M3-W
40              - renesas,ipmmu-r8a77961 # R-Car M3-W+
41              - renesas,ipmmu-r8a77965 # R-Car M3-N
42              - renesas,ipmmu-r8a77970 # R-Car V3M
43              - renesas,ipmmu-r8a77980 # R-Car V3H
44              - renesas,ipmmu-r8a77990 # R-Car E3
45              - renesas,ipmmu-r8a77995 # R-Car D3
46
47  reg:
48    maxItems: 1
49
50  interrupts:
51    minItems: 1
52    description:
53      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
54    items:
55      - description: non-secure mode
56      - description: secure mode if supported
57
58  '#iommu-cells':
59    const: 1
60    description:
61      The number of the micro-TLB that the device is connected to.
62
63  power-domains:
64    maxItems: 1
65
66  renesas,ipmmu-main:
67    $ref: /schemas/types.yaml#/definitions/phandle-array
68    description:
69      Reference to the main IPMMU phandle plus 1 cell. The cell is
70      the interrupt bit number associated with the particular cache IPMMU
71      device. The interrupt bit number needs to match the main IPMMU IMSSTR
72      register. Only used by cache IPMMU instances.
73
74required:
75  - compatible
76  - reg
77  - '#iommu-cells'
78
79oneOf:
80  - required:
81      - interrupts
82  - required:
83      - renesas,ipmmu-main
84
85additionalProperties: false
86
87allOf:
88  - if:
89      properties:
90        compatible:
91          not:
92            contains:
93              const: renesas,ipmmu-vmsa
94    then:
95      required:
96        - power-domains
97
98examples:
99  - |
100    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102    #include <dt-bindings/power/r8a7791-sysc.h>
103
104    ipmmu_mx: iommu@fe951000 {
105        compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
106        reg = <0xfe951000 0x1000>;
107        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
109        #iommu-cells = <1>;
110    };
111