1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies legacy IOMMU implementations
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@linaro.org>
11
12description: |
13  Qualcomm "B" family devices which are not compatible with arm-smmu have
14  a similar looking IOMMU, but without access to the global register space
15  and optionally requiring additional configuration to route context IRQs
16  to non-secure vs secure interrupt line.
17
18properties:
19  compatible:
20    items:
21      - enum:
22          - qcom,msm8916-iommu
23          - qcom,msm8953-iommu
24      - const: qcom,msm-iommu-v1
25
26  clocks:
27    items:
28      - description: Clock required for IOMMU register group access
29      - description: Clock required for underlying bus access
30
31  clock-names:
32    items:
33      - const: iface
34      - const: bus
35
36  power-domains:
37    maxItems: 1
38
39  reg:
40    maxItems: 1
41
42  ranges: true
43
44  qcom,iommu-secure-id:
45    $ref: /schemas/types.yaml#/definitions/uint32
46    description:
47      The SCM secure ID of the IOMMU instance.
48
49  '#address-cells':
50    const: 1
51
52  '#size-cells':
53    const: 1
54
55  '#iommu-cells':
56    const: 1
57
58patternProperties:
59  "^iommu-ctx@[0-9a-f]+$":
60    type: object
61    additionalProperties: false
62    properties:
63      compatible:
64        enum:
65          - qcom,msm-iommu-v1-ns
66          - qcom,msm-iommu-v1-sec
67
68      interrupts:
69        maxItems: 1
70
71      reg:
72        maxItems: 1
73
74      qcom,ctx-asid:
75        $ref: /schemas/types.yaml#/definitions/uint32
76        description:
77          The ASID number associated to the context bank.
78
79    required:
80      - compatible
81      - interrupts
82      - reg
83
84required:
85  - compatible
86  - clocks
87  - clock-names
88  - ranges
89  - '#address-cells'
90  - '#size-cells'
91  - '#iommu-cells'
92
93additionalProperties: false
94
95examples:
96  - |
97    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
98    #include <dt-bindings/interrupt-controller/arm-gic.h>
99
100    apps_iommu: iommu@1e20000 {
101      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
102      reg = <0x01ef0000 0x3000>;
103      clocks = <&gcc GCC_SMMU_CFG_CLK>,
104               <&gcc GCC_APSS_TCU_CLK>;
105      clock-names = "iface", "bus";
106      qcom,iommu-secure-id = <17>;
107      #address-cells = <1>;
108      #size-cells = <1>;
109      #iommu-cells = <1>;
110      ranges = <0 0x01e20000 0x40000>;
111
112      /* mdp_0: */
113      iommu-ctx@4000 {
114        compatible = "qcom,msm-iommu-v1-ns";
115        reg = <0x4000 0x1000>;
116        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
117      };
118    };
119