1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek IOMMU Architecture Implementation
8
9maintainers:
10  - Yong Wu <yong.wu@mediatek.com>
11
12description: |+
13  Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
14  this M4U have two generations of HW architecture. Generation one uses flat
15  pagetable, and only supports 4K size page mapping. Generation two uses the
16  ARM Short-Descriptor translation table format for address translation.
17
18  About the M4U Hardware Block Diagram, please check below:
19
20                EMI (External Memory Interface)
21                 |
22                m4u (Multimedia Memory Management Unit)
23                 |
24            +--------+
25            |        |
26        gals0-rx   gals1-rx    (Global Async Local Sync rx)
27            |        |
28            |        |
29        gals0-tx   gals1-tx    (Global Async Local Sync tx)
30            |        |          Some SoCs may have GALS.
31            +--------+
32                 |
33             SMI Common(Smart Multimedia Interface Common)
34                 |
35         +----------------+-------
36         |                |
37         |             gals-rx        There may be GALS in some larbs.
38         |                |
39         |                |
40         |             gals-tx
41         |                |
42     SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).
43     (display)         (vdec)
44         |                |
45         |                |
46   +-----+-----+     +----+----+
47   |     |     |     |    |    |
48   |     |     |...  |    |    |  ... There are different ports in each larb.
49   |     |     |     |    |    |
50  OVL0 RDMA0 WDMA0  MC   PP   VLD
51
52  As above, The Multimedia HW will go through SMI and M4U while it
53  access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
54  smi local arbiter and smi common. It will control whether the Multimedia
55  HW should go though the m4u for translation or bypass it and talk
56  directly with EMI. And also SMI help control the power domain and clocks for
57  each local arbiter.
58
59  Normally we specify a local arbiter(larb) for each multimedia HW
60  like display, video decode, and camera. And there are different ports
61  in each larb. Take a example, There are many ports like MC, PP, VLD in the
62  video decode local arbiter, all these ports are according to the video HW.
63
64  In some SoCs, there may be a GALS(Global Async Local Sync) module between
65  smi-common and m4u, and additional GALS module between smi-larb and
66  smi-common. GALS can been seen as a "asynchronous fifo" which could help
67  synchronize for the modules in different clock frequency.
68
69properties:
70  compatible:
71    oneOf:
72      - enum:
73          - mediatek,mt2701-m4u  # generation one
74          - mediatek,mt2712-m4u  # generation two
75          - mediatek,mt6779-m4u  # generation two
76          - mediatek,mt8167-m4u  # generation two
77          - mediatek,mt8173-m4u  # generation two
78          - mediatek,mt8183-m4u  # generation two
79          - mediatek,mt8186-iommu-mm         # generation two
80          - mediatek,mt8192-m4u  # generation two
81          - mediatek,mt8195-iommu-vdo        # generation two
82          - mediatek,mt8195-iommu-vpp        # generation two
83          - mediatek,mt8195-iommu-infra      # generation two
84
85      - description: mt7623 generation one
86        items:
87          - const: mediatek,mt7623-m4u
88          - const: mediatek,mt2701-m4u
89
90  reg:
91    maxItems: 1
92
93  interrupts:
94    maxItems: 1
95
96  clocks:
97    items:
98      - description: bclk is the block clock.
99
100  clock-names:
101    items:
102      - const: bclk
103
104  mediatek,larbs:
105    $ref: /schemas/types.yaml#/definitions/phandle-array
106    minItems: 1
107    maxItems: 32
108    items:
109      maxItems: 1
110    description: |
111      List of phandle to the local arbiters in the current Socs.
112      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
113      according to the local arbiter index, like larb0, larb1, larb2...
114
115  '#iommu-cells':
116    const: 1
117    description: |
118      This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
119      defined in
120      dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
121      dt-binding/memory/mt2712-larb-port.h for mt2712,
122      dt-binding/memory/mt6779-larb-port.h for mt6779,
123      dt-binding/memory/mt8167-larb-port.h for mt8167,
124      dt-binding/memory/mt8173-larb-port.h for mt8173,
125      dt-binding/memory/mt8183-larb-port.h for mt8183,
126      dt-binding/memory/mt8186-memory-port.h for mt8186,
127      dt-binding/memory/mt8192-larb-port.h for mt8192.
128      dt-binding/memory/mt8195-memory-port.h for mt8195.
129
130  power-domains:
131    maxItems: 1
132
133required:
134  - compatible
135  - reg
136  - interrupts
137  - '#iommu-cells'
138
139allOf:
140  - if:
141      properties:
142        compatible:
143          contains:
144            enum:
145              - mediatek,mt2701-m4u
146              - mediatek,mt2712-m4u
147              - mediatek,mt8173-m4u
148              - mediatek,mt8186-iommu-mm
149              - mediatek,mt8192-m4u
150              - mediatek,mt8195-iommu-vdo
151              - mediatek,mt8195-iommu-vpp
152
153    then:
154      required:
155        - clocks
156
157  - if:
158      properties:
159        compatible:
160          enum:
161            - mediatek,mt8186-iommu-mm
162            - mediatek,mt8192-m4u
163            - mediatek,mt8195-iommu-vdo
164            - mediatek,mt8195-iommu-vpp
165
166    then:
167      required:
168        - power-domains
169
170  - if: # The IOMMUs don't have larbs.
171      not:
172        properties:
173          compatible:
174            contains:
175              const: mediatek,mt8195-iommu-infra
176
177    then:
178      required:
179        - mediatek,larbs
180
181additionalProperties: false
182
183examples:
184  - |
185    #include <dt-bindings/clock/mt8173-clk.h>
186    #include <dt-bindings/interrupt-controller/arm-gic.h>
187
188    iommu: iommu@10205000 {
189            compatible = "mediatek,mt8173-m4u";
190            reg = <0x10205000 0x1000>;
191            interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
192            clocks = <&infracfg CLK_INFRA_M4U>;
193            clock-names = "bclk";
194            mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
195                             <&larb3>, <&larb4>, <&larb5>;
196            #iommu-cells = <1>;
197    };
198