1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek IOMMU Architecture Implementation
8
9maintainers:
10  - Yong Wu <yong.wu@mediatek.com>
11
12description: |+
13  Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
14  this M4U have two generations of HW architecture. Generation one uses flat
15  pagetable, and only supports 4K size page mapping. Generation two uses the
16  ARM Short-Descriptor translation table format for address translation.
17
18  About the M4U Hardware Block Diagram, please check below:
19
20                EMI (External Memory Interface)
21                 |
22                m4u (Multimedia Memory Management Unit)
23                 |
24            +--------+
25            |        |
26        gals0-rx   gals1-rx    (Global Async Local Sync rx)
27            |        |
28            |        |
29        gals0-tx   gals1-tx    (Global Async Local Sync tx)
30            |        |          Some SoCs may have GALS.
31            +--------+
32                 |
33             SMI Common(Smart Multimedia Interface Common)
34                 |
35         +----------------+-------
36         |                |
37         |             gals-rx        There may be GALS in some larbs.
38         |                |
39         |                |
40         |             gals-tx
41         |                |
42     SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).
43     (display)         (vdec)
44         |                |
45         |                |
46   +-----+-----+     +----+----+
47   |     |     |     |    |    |
48   |     |     |...  |    |    |  ... There are different ports in each larb.
49   |     |     |     |    |    |
50  OVL0 RDMA0 WDMA0  MC   PP   VLD
51
52  As above, The Multimedia HW will go through SMI and M4U while it
53  access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
54  smi local arbiter and smi common. It will control whether the Multimedia
55  HW should go though the m4u for translation or bypass it and talk
56  directly with EMI. And also SMI help control the power domain and clocks for
57  each local arbiter.
58
59  Normally we specify a local arbiter(larb) for each multimedia HW
60  like display, video decode, and camera. And there are different ports
61  in each larb. Take a example, There are many ports like MC, PP, VLD in the
62  video decode local arbiter, all these ports are according to the video HW.
63
64  In some SoCs, there may be a GALS(Global Async Local Sync) module between
65  smi-common and m4u, and additional GALS module between smi-larb and
66  smi-common. GALS can been seen as a "asynchronous fifo" which could help
67  synchronize for the modules in different clock frequency.
68
69properties:
70  compatible:
71    oneOf:
72      - enum:
73          - mediatek,mt2701-m4u  # generation one
74          - mediatek,mt2712-m4u  # generation two
75          - mediatek,mt6779-m4u  # generation two
76          - mediatek,mt6795-m4u  # generation two
77          - mediatek,mt8167-m4u  # generation two
78          - mediatek,mt8173-m4u  # generation two
79          - mediatek,mt8183-m4u  # generation two
80          - mediatek,mt8186-iommu-mm         # generation two
81          - mediatek,mt8192-m4u  # generation two
82          - mediatek,mt8195-iommu-vdo        # generation two
83          - mediatek,mt8195-iommu-vpp        # generation two
84          - mediatek,mt8195-iommu-infra      # generation two
85
86      - description: mt7623 generation one
87        items:
88          - const: mediatek,mt7623-m4u
89          - const: mediatek,mt2701-m4u
90
91  reg:
92    maxItems: 1
93
94  interrupts:
95    maxItems: 1
96
97  clocks:
98    items:
99      - description: bclk is the block clock.
100
101  clock-names:
102    items:
103      - const: bclk
104
105  mediatek,infracfg:
106    $ref: /schemas/types.yaml#/definitions/phandle
107    description: The phandle to the mediatek infracfg syscon
108
109  mediatek,larbs:
110    $ref: /schemas/types.yaml#/definitions/phandle-array
111    minItems: 1
112    maxItems: 32
113    items:
114      maxItems: 1
115    description: |
116      List of phandle to the local arbiters in the current Socs.
117      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
118      according to the local arbiter index, like larb0, larb1, larb2...
119
120  '#iommu-cells':
121    const: 1
122    description: |
123      This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
124      defined in
125      dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
126      dt-binding/memory/mt2712-larb-port.h for mt2712,
127      dt-binding/memory/mt6779-larb-port.h for mt6779,
128      dt-binding/memory/mt6795-larb-port.h for mt6795,
129      dt-binding/memory/mt8167-larb-port.h for mt8167,
130      dt-binding/memory/mt8173-larb-port.h for mt8173,
131      dt-binding/memory/mt8183-larb-port.h for mt8183,
132      dt-binding/memory/mt8186-memory-port.h for mt8186,
133      dt-binding/memory/mt8192-larb-port.h for mt8192.
134      dt-binding/memory/mt8195-memory-port.h for mt8195.
135
136  power-domains:
137    maxItems: 1
138
139required:
140  - compatible
141  - reg
142  - interrupts
143  - '#iommu-cells'
144
145allOf:
146  - if:
147      properties:
148        compatible:
149          contains:
150            enum:
151              - mediatek,mt2701-m4u
152              - mediatek,mt2712-m4u
153              - mediatek,mt6795-m4u
154              - mediatek,mt8173-m4u
155              - mediatek,mt8186-iommu-mm
156              - mediatek,mt8192-m4u
157              - mediatek,mt8195-iommu-vdo
158              - mediatek,mt8195-iommu-vpp
159
160    then:
161      required:
162        - clocks
163
164  - if:
165      properties:
166        compatible:
167          enum:
168            - mediatek,mt8186-iommu-mm
169            - mediatek,mt8192-m4u
170            - mediatek,mt8195-iommu-vdo
171            - mediatek,mt8195-iommu-vpp
172
173    then:
174      required:
175        - power-domains
176
177  - if:
178      properties:
179        compatible:
180          contains:
181            enum:
182              - mediatek,mt2712-m4u
183              - mediatek,mt6795-m4u
184              - mediatek,mt8173-m4u
185
186    then:
187      required:
188        - mediatek,infracfg
189
190  - if: # The IOMMUs don't have larbs.
191      not:
192        properties:
193          compatible:
194            contains:
195              const: mediatek,mt8195-iommu-infra
196
197    then:
198      required:
199        - mediatek,larbs
200
201additionalProperties: false
202
203examples:
204  - |
205    #include <dt-bindings/clock/mt8173-clk.h>
206    #include <dt-bindings/interrupt-controller/arm-gic.h>
207
208    iommu: iommu@10205000 {
209            compatible = "mediatek,mt8173-m4u";
210            reg = <0x10205000 0x1000>;
211            interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
212            clocks = <&infracfg CLK_INFRA_M4U>;
213            clock-names = "bclk";
214            mediatek,infracfg = <&infracfg>;
215            mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
216                             <&larb3>, <&larb4>, <&larb5>;
217            #iommu-cells = <1>;
218    };
219