1bca28426SYong Wu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2bca28426SYong Wu%YAML 1.2 3bca28426SYong Wu--- 4bca28426SYong Wu$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5bca28426SYong Wu$schema: http://devicetree.org/meta-schemas/core.yaml# 6bca28426SYong Wu 7bca28426SYong Wutitle: MediaTek IOMMU Architecture Implementation 8bca28426SYong Wu 9bca28426SYong Wumaintainers: 10bca28426SYong Wu - Yong Wu <yong.wu@mediatek.com> 11bca28426SYong Wu 12bca28426SYong Wudescription: |+ 13bca28426SYong Wu Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14bca28426SYong Wu this M4U have two generations of HW architecture. Generation one uses flat 15bca28426SYong Wu pagetable, and only supports 4K size page mapping. Generation two uses the 16bca28426SYong Wu ARM Short-Descriptor translation table format for address translation. 17bca28426SYong Wu 18bca28426SYong Wu About the M4U Hardware Block Diagram, please check below: 19bca28426SYong Wu 20bca28426SYong Wu EMI (External Memory Interface) 21bca28426SYong Wu | 22bca28426SYong Wu m4u (Multimedia Memory Management Unit) 23bca28426SYong Wu | 24bca28426SYong Wu +--------+ 25bca28426SYong Wu | | 26bca28426SYong Wu gals0-rx gals1-rx (Global Async Local Sync rx) 27bca28426SYong Wu | | 28bca28426SYong Wu | | 29bca28426SYong Wu gals0-tx gals1-tx (Global Async Local Sync tx) 30bca28426SYong Wu | | Some SoCs may have GALS. 31bca28426SYong Wu +--------+ 32bca28426SYong Wu | 33bca28426SYong Wu SMI Common(Smart Multimedia Interface Common) 34bca28426SYong Wu | 35bca28426SYong Wu +----------------+------- 36bca28426SYong Wu | | 37bca28426SYong Wu | gals-rx There may be GALS in some larbs. 38bca28426SYong Wu | | 39bca28426SYong Wu | | 40bca28426SYong Wu | gals-tx 41bca28426SYong Wu | | 42bca28426SYong Wu SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43bca28426SYong Wu (display) (vdec) 44bca28426SYong Wu | | 45bca28426SYong Wu | | 46bca28426SYong Wu +-----+-----+ +----+----+ 47bca28426SYong Wu | | | | | | 48bca28426SYong Wu | | |... | | | ... There are different ports in each larb. 49bca28426SYong Wu | | | | | | 50bca28426SYong Wu OVL0 RDMA0 WDMA0 MC PP VLD 51bca28426SYong Wu 52bca28426SYong Wu As above, The Multimedia HW will go through SMI and M4U while it 53bca28426SYong Wu access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54bca28426SYong Wu smi local arbiter and smi common. It will control whether the Multimedia 55bca28426SYong Wu HW should go though the m4u for translation or bypass it and talk 56bca28426SYong Wu directly with EMI. And also SMI help control the power domain and clocks for 57bca28426SYong Wu each local arbiter. 58bca28426SYong Wu 59bca28426SYong Wu Normally we specify a local arbiter(larb) for each multimedia HW 60bca28426SYong Wu like display, video decode, and camera. And there are different ports 61bca28426SYong Wu in each larb. Take a example, There are many ports like MC, PP, VLD in the 62bca28426SYong Wu video decode local arbiter, all these ports are according to the video HW. 63bca28426SYong Wu 64bca28426SYong Wu In some SoCs, there may be a GALS(Global Async Local Sync) module between 65bca28426SYong Wu smi-common and m4u, and additional GALS module between smi-larb and 66bca28426SYong Wu smi-common. GALS can been seen as a "asynchronous fifo" which could help 67bca28426SYong Wu synchronize for the modules in different clock frequency. 68bca28426SYong Wu 69bca28426SYong Wuproperties: 70bca28426SYong Wu compatible: 71bca28426SYong Wu oneOf: 72bca28426SYong Wu - enum: 73bca28426SYong Wu - mediatek,mt2701-m4u # generation one 74bca28426SYong Wu - mediatek,mt2712-m4u # generation two 75bca28426SYong Wu - mediatek,mt6779-m4u # generation two 764e5f8465SAngeloGioacchino Del Regno - mediatek,mt6795-m4u # generation two 77bca28426SYong Wu - mediatek,mt8167-m4u # generation two 78bca28426SYong Wu - mediatek,mt8173-m4u # generation two 79bca28426SYong Wu - mediatek,mt8183-m4u # generation two 802d555a38SYong Wu - mediatek,mt8186-iommu-mm # generation two 81*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vdo # generation two 82*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vpp # generation two 83*d5cda142SChengci.Xu - mediatek,mt8188-iommu-infra # generation two 84fc373469SYong Wu - mediatek,mt8192-m4u # generation two 856625ffb9SYong Wu - mediatek,mt8195-iommu-vdo # generation two 866625ffb9SYong Wu - mediatek,mt8195-iommu-vpp # generation two 87dc1d9934SYong Wu - mediatek,mt8195-iommu-infra # generation two 8859a316fdSFabien Parent - mediatek,mt8365-m4u # generation two 89bca28426SYong Wu 90bca28426SYong Wu - description: mt7623 generation one 91bca28426SYong Wu items: 92bca28426SYong Wu - const: mediatek,mt7623-m4u 93bca28426SYong Wu - const: mediatek,mt2701-m4u 94bca28426SYong Wu 95bca28426SYong Wu reg: 96bca28426SYong Wu maxItems: 1 97bca28426SYong Wu 98bca28426SYong Wu interrupts: 99bca28426SYong Wu maxItems: 1 100bca28426SYong Wu 101bca28426SYong Wu clocks: 102bca28426SYong Wu items: 103bca28426SYong Wu - description: bclk is the block clock. 104bca28426SYong Wu 105bca28426SYong Wu clock-names: 106bca28426SYong Wu items: 107bca28426SYong Wu - const: bclk 108bca28426SYong Wu 109d034dbbbSAngeloGioacchino Del Regno mediatek,infracfg: 110d034dbbbSAngeloGioacchino Del Regno $ref: /schemas/types.yaml#/definitions/phandle 111d034dbbbSAngeloGioacchino Del Regno description: The phandle to the mediatek infracfg syscon 112d034dbbbSAngeloGioacchino Del Regno 113bca28426SYong Wu mediatek,larbs: 114bca28426SYong Wu $ref: /schemas/types.yaml#/definitions/phandle-array 115bca28426SYong Wu minItems: 1 116ca49a4b4SYong Wu maxItems: 32 11739bd2b6aSRob Herring items: 11839bd2b6aSRob Herring maxItems: 1 119bca28426SYong Wu description: | 120bca28426SYong Wu List of phandle to the local arbiters in the current Socs. 121bca28426SYong Wu Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 122bca28426SYong Wu according to the local arbiter index, like larb0, larb1, larb2... 123bca28426SYong Wu 124bca28426SYong Wu '#iommu-cells': 125bca28426SYong Wu const: 1 126bca28426SYong Wu description: | 127bca28426SYong Wu This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 128bca28426SYong Wu defined in 129*d5cda142SChengci.Xu dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, 130bca28426SYong Wu dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 131bca28426SYong Wu dt-binding/memory/mt2712-larb-port.h for mt2712, 132bca28426SYong Wu dt-binding/memory/mt6779-larb-port.h for mt6779, 1334e5f8465SAngeloGioacchino Del Regno dt-binding/memory/mt6795-larb-port.h for mt6795, 134bca28426SYong Wu dt-binding/memory/mt8167-larb-port.h for mt8167, 135bca28426SYong Wu dt-binding/memory/mt8173-larb-port.h for mt8173, 136fc373469SYong Wu dt-binding/memory/mt8183-larb-port.h for mt8183, 1372d555a38SYong Wu dt-binding/memory/mt8186-memory-port.h for mt8186, 138fc373469SYong Wu dt-binding/memory/mt8192-larb-port.h for mt8192. 1396625ffb9SYong Wu dt-binding/memory/mt8195-memory-port.h for mt8195. 14059a316fdSFabien Parent dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365. 141fc373469SYong Wu 142fc373469SYong Wu power-domains: 143fc373469SYong Wu maxItems: 1 144bca28426SYong Wu 145bca28426SYong Wurequired: 146bca28426SYong Wu - compatible 147bca28426SYong Wu - reg 148bca28426SYong Wu - interrupts 149bca28426SYong Wu - '#iommu-cells' 150bca28426SYong Wu 151bca28426SYong WuallOf: 152bca28426SYong Wu - if: 153bca28426SYong Wu properties: 154bca28426SYong Wu compatible: 155bca28426SYong Wu contains: 156bca28426SYong Wu enum: 157bca28426SYong Wu - mediatek,mt2701-m4u 158bca28426SYong Wu - mediatek,mt2712-m4u 1594e5f8465SAngeloGioacchino Del Regno - mediatek,mt6795-m4u 160bca28426SYong Wu - mediatek,mt8173-m4u 1612d555a38SYong Wu - mediatek,mt8186-iommu-mm 162*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vdo 163*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vpp 164fc373469SYong Wu - mediatek,mt8192-m4u 1656625ffb9SYong Wu - mediatek,mt8195-iommu-vdo 1666625ffb9SYong Wu - mediatek,mt8195-iommu-vpp 167bca28426SYong Wu 168bca28426SYong Wu then: 169bca28426SYong Wu required: 170bca28426SYong Wu - clocks 171bca28426SYong Wu 172fc373469SYong Wu - if: 173fc373469SYong Wu properties: 174fc373469SYong Wu compatible: 175fc373469SYong Wu enum: 1762d555a38SYong Wu - mediatek,mt8186-iommu-mm 177*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vdo 178*d5cda142SChengci.Xu - mediatek,mt8188-iommu-vpp 179fc373469SYong Wu - mediatek,mt8192-m4u 1806625ffb9SYong Wu - mediatek,mt8195-iommu-vdo 1816625ffb9SYong Wu - mediatek,mt8195-iommu-vpp 182fc373469SYong Wu 183fc373469SYong Wu then: 184fc373469SYong Wu required: 185fc373469SYong Wu - power-domains 186fc373469SYong Wu 187d034dbbbSAngeloGioacchino Del Regno - if: 188d034dbbbSAngeloGioacchino Del Regno properties: 189d034dbbbSAngeloGioacchino Del Regno compatible: 190d034dbbbSAngeloGioacchino Del Regno contains: 191d034dbbbSAngeloGioacchino Del Regno enum: 192d034dbbbSAngeloGioacchino Del Regno - mediatek,mt2712-m4u 1934e5f8465SAngeloGioacchino Del Regno - mediatek,mt6795-m4u 194d034dbbbSAngeloGioacchino Del Regno - mediatek,mt8173-m4u 195d034dbbbSAngeloGioacchino Del Regno 196d034dbbbSAngeloGioacchino Del Regno then: 197d034dbbbSAngeloGioacchino Del Regno required: 198d034dbbbSAngeloGioacchino Del Regno - mediatek,infracfg 199d034dbbbSAngeloGioacchino Del Regno 200dc1d9934SYong Wu - if: # The IOMMUs don't have larbs. 201dc1d9934SYong Wu not: 202dc1d9934SYong Wu properties: 203dc1d9934SYong Wu compatible: 204dc1d9934SYong Wu contains: 205*d5cda142SChengci.Xu enum: 206*d5cda142SChengci.Xu - mediatek,mt8188-iommu-infra 207*d5cda142SChengci.Xu - mediatek,mt8195-iommu-infra 208dc1d9934SYong Wu 209dc1d9934SYong Wu then: 210dc1d9934SYong Wu required: 211dc1d9934SYong Wu - mediatek,larbs 212dc1d9934SYong Wu 213bca28426SYong WuadditionalProperties: false 214bca28426SYong Wu 215bca28426SYong Wuexamples: 216bca28426SYong Wu - | 217bca28426SYong Wu #include <dt-bindings/clock/mt8173-clk.h> 218bca28426SYong Wu #include <dt-bindings/interrupt-controller/arm-gic.h> 219bca28426SYong Wu 220bca28426SYong Wu iommu: iommu@10205000 { 221bca28426SYong Wu compatible = "mediatek,mt8173-m4u"; 222bca28426SYong Wu reg = <0x10205000 0x1000>; 223bca28426SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 224bca28426SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 225bca28426SYong Wu clock-names = "bclk"; 226d034dbbbSAngeloGioacchino Del Regno mediatek,infracfg = <&infracfg>; 22739bd2b6aSRob Herring mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 22839bd2b6aSRob Herring <&larb3>, <&larb4>, <&larb5>; 229bca28426SYong Wu #iommu-cells = <1>; 230bca28426SYong Wu }; 231