1bca28426SYong Wu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2bca28426SYong Wu%YAML 1.2 3bca28426SYong Wu--- 4bca28426SYong Wu$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5bca28426SYong Wu$schema: http://devicetree.org/meta-schemas/core.yaml# 6bca28426SYong Wu 7bca28426SYong Wutitle: MediaTek IOMMU Architecture Implementation 8bca28426SYong Wu 9bca28426SYong Wumaintainers: 10bca28426SYong Wu - Yong Wu <yong.wu@mediatek.com> 11bca28426SYong Wu 12bca28426SYong Wudescription: |+ 13bca28426SYong Wu Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14bca28426SYong Wu this M4U have two generations of HW architecture. Generation one uses flat 15bca28426SYong Wu pagetable, and only supports 4K size page mapping. Generation two uses the 16bca28426SYong Wu ARM Short-Descriptor translation table format for address translation. 17bca28426SYong Wu 18bca28426SYong Wu About the M4U Hardware Block Diagram, please check below: 19bca28426SYong Wu 20bca28426SYong Wu EMI (External Memory Interface) 21bca28426SYong Wu | 22bca28426SYong Wu m4u (Multimedia Memory Management Unit) 23bca28426SYong Wu | 24bca28426SYong Wu +--------+ 25bca28426SYong Wu | | 26bca28426SYong Wu gals0-rx gals1-rx (Global Async Local Sync rx) 27bca28426SYong Wu | | 28bca28426SYong Wu | | 29bca28426SYong Wu gals0-tx gals1-tx (Global Async Local Sync tx) 30bca28426SYong Wu | | Some SoCs may have GALS. 31bca28426SYong Wu +--------+ 32bca28426SYong Wu | 33bca28426SYong Wu SMI Common(Smart Multimedia Interface Common) 34bca28426SYong Wu | 35bca28426SYong Wu +----------------+------- 36bca28426SYong Wu | | 37bca28426SYong Wu | gals-rx There may be GALS in some larbs. 38bca28426SYong Wu | | 39bca28426SYong Wu | | 40bca28426SYong Wu | gals-tx 41bca28426SYong Wu | | 42bca28426SYong Wu SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43bca28426SYong Wu (display) (vdec) 44bca28426SYong Wu | | 45bca28426SYong Wu | | 46bca28426SYong Wu +-----+-----+ +----+----+ 47bca28426SYong Wu | | | | | | 48bca28426SYong Wu | | |... | | | ... There are different ports in each larb. 49bca28426SYong Wu | | | | | | 50bca28426SYong Wu OVL0 RDMA0 WDMA0 MC PP VLD 51bca28426SYong Wu 52bca28426SYong Wu As above, The Multimedia HW will go through SMI and M4U while it 53bca28426SYong Wu access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54bca28426SYong Wu smi local arbiter and smi common. It will control whether the Multimedia 55bca28426SYong Wu HW should go though the m4u for translation or bypass it and talk 56bca28426SYong Wu directly with EMI. And also SMI help control the power domain and clocks for 57bca28426SYong Wu each local arbiter. 58bca28426SYong Wu 59bca28426SYong Wu Normally we specify a local arbiter(larb) for each multimedia HW 60bca28426SYong Wu like display, video decode, and camera. And there are different ports 61bca28426SYong Wu in each larb. Take a example, There are many ports like MC, PP, VLD in the 62bca28426SYong Wu video decode local arbiter, all these ports are according to the video HW. 63bca28426SYong Wu 64bca28426SYong Wu In some SoCs, there may be a GALS(Global Async Local Sync) module between 65bca28426SYong Wu smi-common and m4u, and additional GALS module between smi-larb and 66bca28426SYong Wu smi-common. GALS can been seen as a "asynchronous fifo" which could help 67bca28426SYong Wu synchronize for the modules in different clock frequency. 68bca28426SYong Wu 69bca28426SYong Wuproperties: 70bca28426SYong Wu compatible: 71bca28426SYong Wu oneOf: 72bca28426SYong Wu - enum: 73bca28426SYong Wu - mediatek,mt2701-m4u # generation one 74bca28426SYong Wu - mediatek,mt2712-m4u # generation two 75bca28426SYong Wu - mediatek,mt6779-m4u # generation two 76bca28426SYong Wu - mediatek,mt8167-m4u # generation two 77bca28426SYong Wu - mediatek,mt8173-m4u # generation two 78bca28426SYong Wu - mediatek,mt8183-m4u # generation two 792d555a38SYong Wu - mediatek,mt8186-iommu-mm # generation two 80fc373469SYong Wu - mediatek,mt8192-m4u # generation two 816625ffb9SYong Wu - mediatek,mt8195-iommu-vdo # generation two 826625ffb9SYong Wu - mediatek,mt8195-iommu-vpp # generation two 83dc1d9934SYong Wu - mediatek,mt8195-iommu-infra # generation two 84bca28426SYong Wu 85bca28426SYong Wu - description: mt7623 generation one 86bca28426SYong Wu items: 87bca28426SYong Wu - const: mediatek,mt7623-m4u 88bca28426SYong Wu - const: mediatek,mt2701-m4u 89bca28426SYong Wu 90bca28426SYong Wu reg: 91bca28426SYong Wu maxItems: 1 92bca28426SYong Wu 93bca28426SYong Wu interrupts: 94bca28426SYong Wu maxItems: 1 95bca28426SYong Wu 96bca28426SYong Wu clocks: 97bca28426SYong Wu items: 98bca28426SYong Wu - description: bclk is the block clock. 99bca28426SYong Wu 100bca28426SYong Wu clock-names: 101bca28426SYong Wu items: 102bca28426SYong Wu - const: bclk 103bca28426SYong Wu 104*d034dbbbSAngeloGioacchino Del Regno mediatek,infracfg: 105*d034dbbbSAngeloGioacchino Del Regno $ref: /schemas/types.yaml#/definitions/phandle 106*d034dbbbSAngeloGioacchino Del Regno description: The phandle to the mediatek infracfg syscon 107*d034dbbbSAngeloGioacchino Del Regno 108bca28426SYong Wu mediatek,larbs: 109bca28426SYong Wu $ref: /schemas/types.yaml#/definitions/phandle-array 110bca28426SYong Wu minItems: 1 111ca49a4b4SYong Wu maxItems: 32 11239bd2b6aSRob Herring items: 11339bd2b6aSRob Herring maxItems: 1 114bca28426SYong Wu description: | 115bca28426SYong Wu List of phandle to the local arbiters in the current Socs. 116bca28426SYong Wu Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 117bca28426SYong Wu according to the local arbiter index, like larb0, larb1, larb2... 118bca28426SYong Wu 119bca28426SYong Wu '#iommu-cells': 120bca28426SYong Wu const: 1 121bca28426SYong Wu description: | 122bca28426SYong Wu This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 123bca28426SYong Wu defined in 124bca28426SYong Wu dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 125bca28426SYong Wu dt-binding/memory/mt2712-larb-port.h for mt2712, 126bca28426SYong Wu dt-binding/memory/mt6779-larb-port.h for mt6779, 127bca28426SYong Wu dt-binding/memory/mt8167-larb-port.h for mt8167, 128bca28426SYong Wu dt-binding/memory/mt8173-larb-port.h for mt8173, 129fc373469SYong Wu dt-binding/memory/mt8183-larb-port.h for mt8183, 1302d555a38SYong Wu dt-binding/memory/mt8186-memory-port.h for mt8186, 131fc373469SYong Wu dt-binding/memory/mt8192-larb-port.h for mt8192. 1326625ffb9SYong Wu dt-binding/memory/mt8195-memory-port.h for mt8195. 133fc373469SYong Wu 134fc373469SYong Wu power-domains: 135fc373469SYong Wu maxItems: 1 136bca28426SYong Wu 137bca28426SYong Wurequired: 138bca28426SYong Wu - compatible 139bca28426SYong Wu - reg 140bca28426SYong Wu - interrupts 141bca28426SYong Wu - '#iommu-cells' 142bca28426SYong Wu 143bca28426SYong WuallOf: 144bca28426SYong Wu - if: 145bca28426SYong Wu properties: 146bca28426SYong Wu compatible: 147bca28426SYong Wu contains: 148bca28426SYong Wu enum: 149bca28426SYong Wu - mediatek,mt2701-m4u 150bca28426SYong Wu - mediatek,mt2712-m4u 151bca28426SYong Wu - mediatek,mt8173-m4u 1522d555a38SYong Wu - mediatek,mt8186-iommu-mm 153fc373469SYong Wu - mediatek,mt8192-m4u 1546625ffb9SYong Wu - mediatek,mt8195-iommu-vdo 1556625ffb9SYong Wu - mediatek,mt8195-iommu-vpp 156bca28426SYong Wu 157bca28426SYong Wu then: 158bca28426SYong Wu required: 159bca28426SYong Wu - clocks 160bca28426SYong Wu 161fc373469SYong Wu - if: 162fc373469SYong Wu properties: 163fc373469SYong Wu compatible: 164fc373469SYong Wu enum: 1652d555a38SYong Wu - mediatek,mt8186-iommu-mm 166fc373469SYong Wu - mediatek,mt8192-m4u 1676625ffb9SYong Wu - mediatek,mt8195-iommu-vdo 1686625ffb9SYong Wu - mediatek,mt8195-iommu-vpp 169fc373469SYong Wu 170fc373469SYong Wu then: 171fc373469SYong Wu required: 172fc373469SYong Wu - power-domains 173fc373469SYong Wu 174*d034dbbbSAngeloGioacchino Del Regno - if: 175*d034dbbbSAngeloGioacchino Del Regno properties: 176*d034dbbbSAngeloGioacchino Del Regno compatible: 177*d034dbbbSAngeloGioacchino Del Regno contains: 178*d034dbbbSAngeloGioacchino Del Regno enum: 179*d034dbbbSAngeloGioacchino Del Regno - mediatek,mt2712-m4u 180*d034dbbbSAngeloGioacchino Del Regno - mediatek,mt8173-m4u 181*d034dbbbSAngeloGioacchino Del Regno 182*d034dbbbSAngeloGioacchino Del Regno then: 183*d034dbbbSAngeloGioacchino Del Regno required: 184*d034dbbbSAngeloGioacchino Del Regno - mediatek,infracfg 185*d034dbbbSAngeloGioacchino Del Regno 186dc1d9934SYong Wu - if: # The IOMMUs don't have larbs. 187dc1d9934SYong Wu not: 188dc1d9934SYong Wu properties: 189dc1d9934SYong Wu compatible: 190dc1d9934SYong Wu contains: 191dc1d9934SYong Wu const: mediatek,mt8195-iommu-infra 192dc1d9934SYong Wu 193dc1d9934SYong Wu then: 194dc1d9934SYong Wu required: 195dc1d9934SYong Wu - mediatek,larbs 196dc1d9934SYong Wu 197bca28426SYong WuadditionalProperties: false 198bca28426SYong Wu 199bca28426SYong Wuexamples: 200bca28426SYong Wu - | 201bca28426SYong Wu #include <dt-bindings/clock/mt8173-clk.h> 202bca28426SYong Wu #include <dt-bindings/interrupt-controller/arm-gic.h> 203bca28426SYong Wu 204bca28426SYong Wu iommu: iommu@10205000 { 205bca28426SYong Wu compatible = "mediatek,mt8173-m4u"; 206bca28426SYong Wu reg = <0x10205000 0x1000>; 207bca28426SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 208bca28426SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 209bca28426SYong Wu clock-names = "bclk"; 210*d034dbbbSAngeloGioacchino Del Regno mediatek,infracfg = <&infracfg>; 21139bd2b6aSRob Herring mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 21239bd2b6aSRob Herring <&larb3>, <&larb4>, <&larb5>; 213bca28426SYong Wu #iommu-cells = <1>; 214bca28426SYong Wu }; 215