1*bca28426SYong Wu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*bca28426SYong Wu%YAML 1.2 3*bca28426SYong Wu--- 4*bca28426SYong Wu$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5*bca28426SYong Wu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*bca28426SYong Wu 7*bca28426SYong Wutitle: MediaTek IOMMU Architecture Implementation 8*bca28426SYong Wu 9*bca28426SYong Wumaintainers: 10*bca28426SYong Wu - Yong Wu <yong.wu@mediatek.com> 11*bca28426SYong Wu 12*bca28426SYong Wudescription: |+ 13*bca28426SYong Wu Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14*bca28426SYong Wu this M4U have two generations of HW architecture. Generation one uses flat 15*bca28426SYong Wu pagetable, and only supports 4K size page mapping. Generation two uses the 16*bca28426SYong Wu ARM Short-Descriptor translation table format for address translation. 17*bca28426SYong Wu 18*bca28426SYong Wu About the M4U Hardware Block Diagram, please check below: 19*bca28426SYong Wu 20*bca28426SYong Wu EMI (External Memory Interface) 21*bca28426SYong Wu | 22*bca28426SYong Wu m4u (Multimedia Memory Management Unit) 23*bca28426SYong Wu | 24*bca28426SYong Wu +--------+ 25*bca28426SYong Wu | | 26*bca28426SYong Wu gals0-rx gals1-rx (Global Async Local Sync rx) 27*bca28426SYong Wu | | 28*bca28426SYong Wu | | 29*bca28426SYong Wu gals0-tx gals1-tx (Global Async Local Sync tx) 30*bca28426SYong Wu | | Some SoCs may have GALS. 31*bca28426SYong Wu +--------+ 32*bca28426SYong Wu | 33*bca28426SYong Wu SMI Common(Smart Multimedia Interface Common) 34*bca28426SYong Wu | 35*bca28426SYong Wu +----------------+------- 36*bca28426SYong Wu | | 37*bca28426SYong Wu | gals-rx There may be GALS in some larbs. 38*bca28426SYong Wu | | 39*bca28426SYong Wu | | 40*bca28426SYong Wu | gals-tx 41*bca28426SYong Wu | | 42*bca28426SYong Wu SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43*bca28426SYong Wu (display) (vdec) 44*bca28426SYong Wu | | 45*bca28426SYong Wu | | 46*bca28426SYong Wu +-----+-----+ +----+----+ 47*bca28426SYong Wu | | | | | | 48*bca28426SYong Wu | | |... | | | ... There are different ports in each larb. 49*bca28426SYong Wu | | | | | | 50*bca28426SYong Wu OVL0 RDMA0 WDMA0 MC PP VLD 51*bca28426SYong Wu 52*bca28426SYong Wu As above, The Multimedia HW will go through SMI and M4U while it 53*bca28426SYong Wu access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54*bca28426SYong Wu smi local arbiter and smi common. It will control whether the Multimedia 55*bca28426SYong Wu HW should go though the m4u for translation or bypass it and talk 56*bca28426SYong Wu directly with EMI. And also SMI help control the power domain and clocks for 57*bca28426SYong Wu each local arbiter. 58*bca28426SYong Wu 59*bca28426SYong Wu Normally we specify a local arbiter(larb) for each multimedia HW 60*bca28426SYong Wu like display, video decode, and camera. And there are different ports 61*bca28426SYong Wu in each larb. Take a example, There are many ports like MC, PP, VLD in the 62*bca28426SYong Wu video decode local arbiter, all these ports are according to the video HW. 63*bca28426SYong Wu 64*bca28426SYong Wu In some SoCs, there may be a GALS(Global Async Local Sync) module between 65*bca28426SYong Wu smi-common and m4u, and additional GALS module between smi-larb and 66*bca28426SYong Wu smi-common. GALS can been seen as a "asynchronous fifo" which could help 67*bca28426SYong Wu synchronize for the modules in different clock frequency. 68*bca28426SYong Wu 69*bca28426SYong Wuproperties: 70*bca28426SYong Wu compatible: 71*bca28426SYong Wu oneOf: 72*bca28426SYong Wu - enum: 73*bca28426SYong Wu - mediatek,mt2701-m4u # generation one 74*bca28426SYong Wu - mediatek,mt2712-m4u # generation two 75*bca28426SYong Wu - mediatek,mt6779-m4u # generation two 76*bca28426SYong Wu - mediatek,mt8167-m4u # generation two 77*bca28426SYong Wu - mediatek,mt8173-m4u # generation two 78*bca28426SYong Wu - mediatek,mt8183-m4u # generation two 79*bca28426SYong Wu 80*bca28426SYong Wu - description: mt7623 generation one 81*bca28426SYong Wu items: 82*bca28426SYong Wu - const: mediatek,mt7623-m4u 83*bca28426SYong Wu - const: mediatek,mt2701-m4u 84*bca28426SYong Wu 85*bca28426SYong Wu reg: 86*bca28426SYong Wu maxItems: 1 87*bca28426SYong Wu 88*bca28426SYong Wu interrupts: 89*bca28426SYong Wu maxItems: 1 90*bca28426SYong Wu 91*bca28426SYong Wu clocks: 92*bca28426SYong Wu items: 93*bca28426SYong Wu - description: bclk is the block clock. 94*bca28426SYong Wu 95*bca28426SYong Wu clock-names: 96*bca28426SYong Wu items: 97*bca28426SYong Wu - const: bclk 98*bca28426SYong Wu 99*bca28426SYong Wu mediatek,larbs: 100*bca28426SYong Wu $ref: /schemas/types.yaml#/definitions/phandle-array 101*bca28426SYong Wu minItems: 1 102*bca28426SYong Wu maxItems: 16 103*bca28426SYong Wu description: | 104*bca28426SYong Wu List of phandle to the local arbiters in the current Socs. 105*bca28426SYong Wu Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 106*bca28426SYong Wu according to the local arbiter index, like larb0, larb1, larb2... 107*bca28426SYong Wu 108*bca28426SYong Wu '#iommu-cells': 109*bca28426SYong Wu const: 1 110*bca28426SYong Wu description: | 111*bca28426SYong Wu This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 112*bca28426SYong Wu defined in 113*bca28426SYong Wu dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 114*bca28426SYong Wu dt-binding/memory/mt2712-larb-port.h for mt2712, 115*bca28426SYong Wu dt-binding/memory/mt6779-larb-port.h for mt6779, 116*bca28426SYong Wu dt-binding/memory/mt8167-larb-port.h for mt8167, 117*bca28426SYong Wu dt-binding/memory/mt8173-larb-port.h for mt8173, 118*bca28426SYong Wu dt-binding/memory/mt8183-larb-port.h for mt8183. 119*bca28426SYong Wu 120*bca28426SYong Wurequired: 121*bca28426SYong Wu - compatible 122*bca28426SYong Wu - reg 123*bca28426SYong Wu - interrupts 124*bca28426SYong Wu - mediatek,larbs 125*bca28426SYong Wu - '#iommu-cells' 126*bca28426SYong Wu 127*bca28426SYong WuallOf: 128*bca28426SYong Wu - if: 129*bca28426SYong Wu properties: 130*bca28426SYong Wu compatible: 131*bca28426SYong Wu contains: 132*bca28426SYong Wu enum: 133*bca28426SYong Wu - mediatek,mt2701-m4u 134*bca28426SYong Wu - mediatek,mt2712-m4u 135*bca28426SYong Wu - mediatek,mt8173-m4u 136*bca28426SYong Wu 137*bca28426SYong Wu then: 138*bca28426SYong Wu required: 139*bca28426SYong Wu - clocks 140*bca28426SYong Wu 141*bca28426SYong WuadditionalProperties: false 142*bca28426SYong Wu 143*bca28426SYong Wuexamples: 144*bca28426SYong Wu - | 145*bca28426SYong Wu #include <dt-bindings/clock/mt8173-clk.h> 146*bca28426SYong Wu #include <dt-bindings/interrupt-controller/arm-gic.h> 147*bca28426SYong Wu 148*bca28426SYong Wu iommu: iommu@10205000 { 149*bca28426SYong Wu compatible = "mediatek,mt8173-m4u"; 150*bca28426SYong Wu reg = <0x10205000 0x1000>; 151*bca28426SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 152*bca28426SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 153*bca28426SYong Wu clock-names = "bclk"; 154*bca28426SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 155*bca28426SYong Wu &larb3 &larb4 &larb5>; 156*bca28426SYong Wu #iommu-cells = <1>; 157*bca28426SYong Wu }; 158*bca28426SYong Wu 159*bca28426SYong Wu - | 160*bca28426SYong Wu #include <dt-bindings/memory/mt8173-larb-port.h> 161*bca28426SYong Wu 162*bca28426SYong Wu /* Example for a client device */ 163*bca28426SYong Wu display { 164*bca28426SYong Wu compatible = "mediatek,mt8173-disp"; 165*bca28426SYong Wu iommus = <&iommu M4U_PORT_DISP_OVL0>, 166*bca28426SYong Wu <&iommu M4U_PORT_DISP_RDMA0>; 167*bca28426SYong Wu }; 168