1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31              - qcom,sdm630-smmu-v2
32          - const: qcom,smmu-v2
33
34      - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
35        items:
36          - enum:
37              - qcom,qcm2290-smmu-500
38              - qcom,qdu1000-smmu-500
39              - qcom,sc7180-smmu-500
40              - qcom,sc7280-smmu-500
41              - qcom,sc8180x-smmu-500
42              - qcom,sc8280xp-smmu-500
43              - qcom,sdm670-smmu-500
44              - qcom,sdm845-smmu-500
45              - qcom,sm6115-smmu-500
46              - qcom,sm6350-smmu-500
47              - qcom,sm6375-smmu-500
48              - qcom,sm8150-smmu-500
49              - qcom,sm8250-smmu-500
50              - qcom,sm8350-smmu-500
51              - qcom,sm8450-smmu-500
52          - const: qcom,smmu-500
53          - const: arm,mmu-500
54
55      - description: Qcom SoCs implementing "arm,mmu-500" (non-qcom implementation)
56        deprecated: true
57        items:
58          - enum:
59              - qcom,sdx55-smmu-500
60              - qcom,sdx65-smmu-500
61          - const: arm,mmu-500
62
63      - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
64        deprecated: true
65        items:
66          # Do not add additional SoC to this list. Instead use two previous lists.
67          - enum:
68              - qcom,qcm2290-smmu-500
69              - qcom,sc7180-smmu-500
70              - qcom,sc7280-smmu-500
71              - qcom,sc8180x-smmu-500
72              - qcom,sc8280xp-smmu-500
73              - qcom,sdm845-smmu-500
74              - qcom,sm6115-smmu-500
75              - qcom,sm6350-smmu-500
76              - qcom,sm6375-smmu-500
77              - qcom,sm8150-smmu-500
78              - qcom,sm8250-smmu-500
79              - qcom,sm8350-smmu-500
80              - qcom,sm8450-smmu-500
81          - const: arm,mmu-500
82
83      - description: Qcom Adreno GPUs implementing "arm,smmu-500"
84        items:
85          - enum:
86              - qcom,sc7280-smmu-500
87              - qcom,sm8250-smmu-500
88          - const: qcom,adreno-smmu
89          - const: arm,mmu-500
90      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
91        items:
92          - enum:
93              - qcom,msm8996-smmu-v2
94              - qcom,sc7180-smmu-v2
95              - qcom,sdm630-smmu-v2
96              - qcom,sdm845-smmu-v2
97              - qcom,sm6350-smmu-v2
98          - const: qcom,adreno-smmu
99          - const: qcom,smmu-v2
100      - description: Qcom Adreno GPUs on Google Cheza platform
101        items:
102          - const: qcom,sdm845-smmu-v2
103          - const: qcom,smmu-v2
104      - description: Marvell SoCs implementing "arm,mmu-500"
105        items:
106          - const: marvell,ap806-smmu-500
107          - const: arm,mmu-500
108      - description: NVIDIA SoCs that require memory controller interaction
109          and may program multiple ARM MMU-500s identically with the memory
110          controller interleaving translations between multiple instances
111          for improved performance.
112        items:
113          - enum:
114              - nvidia,tegra186-smmu
115              - nvidia,tegra194-smmu
116              - nvidia,tegra234-smmu
117          - const: nvidia,smmu-500
118      - items:
119          - const: arm,mmu-500
120          - const: arm,smmu-v2
121      - items:
122          - enum:
123              - arm,mmu-400
124              - arm,mmu-401
125          - const: arm,smmu-v1
126      - enum:
127          - arm,smmu-v1
128          - arm,smmu-v2
129          - arm,mmu-400
130          - arm,mmu-401
131          - arm,mmu-500
132          - cavium,smmu-v2
133
134  reg:
135    minItems: 1
136    maxItems: 2
137
138  '#global-interrupts':
139    description: The number of global interrupts exposed by the device.
140    $ref: /schemas/types.yaml#/definitions/uint32
141    minimum: 0
142    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
143
144  '#iommu-cells':
145    enum: [ 1, 2 ]
146    description: |
147      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
148      value of 1, each IOMMU specifier represents a distinct stream ID emitted
149      by that device into the relevant SMMU.
150
151      SMMUs with stream matching support and complex masters may use a value of
152      2, where the second cell of the IOMMU specifier represents an SMR mask to
153      combine with the ID in the first cell.  Care must be taken to ensure the
154      set of matched IDs does not result in conflicts.
155
156  interrupts:
157    minItems: 1
158    maxItems: 388   # 260 plus 128 contexts
159    description: |
160      Interrupt list, with the first #global-interrupts entries corresponding to
161      the global interrupts and any following entries corresponding to context
162      interrupts, specified in order of their indexing by the SMMU.
163
164      For SMMUv2 implementations, there must be exactly one interrupt per
165      context bank. In the case of a single, combined interrupt, it must be
166      listed multiple times.
167
168  dma-coherent:
169    description: |
170      Present if page table walks made by the SMMU are cache coherent with the
171      CPU.
172
173      NOTE: this only applies to the SMMU itself, not masters connected
174      upstream of the SMMU.
175
176  calxeda,smmu-secure-config-access:
177    type: boolean
178    description:
179      Enable proper handling of buggy implementations that always use secure
180      access to SMMU configuration registers. In this case non-secure aliases of
181      secure registers have to be used during SMMU configuration.
182
183  stream-match-mask:
184    $ref: /schemas/types.yaml#/definitions/uint32
185    description: |
186      For SMMUs supporting stream matching and using #iommu-cells = <1>,
187      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
188      be programmed into the SMRn.MASK field of every stream match register
189      used). For cases where it is desirable to ignore some portion of every
190      Stream ID (e.g. for certain MMU-500 configurations given globally unique
191      input IDs). This property is not valid for SMMUs using stream indexing, or
192      using stream matching with #iommu-cells = <2>, and may be ignored if
193      present in such cases.
194
195  clock-names:
196    minItems: 1
197    maxItems: 7
198
199  clocks:
200    minItems: 1
201    maxItems: 7
202
203  power-domains:
204    maxItems: 1
205
206  nvidia,memory-controller:
207    description: |
208      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
209      The memory controller needs to be programmed with a mapping of memory
210      client IDs to ARM SMMU stream IDs.
211
212      If this property is absent, the mapping programmed by early firmware
213      will be used and it is not guaranteed that IOMMU translations will be
214      enabled for any given device.
215    $ref: /schemas/types.yaml#/definitions/phandle
216
217required:
218  - compatible
219  - reg
220  - '#global-interrupts'
221  - '#iommu-cells'
222  - interrupts
223
224additionalProperties: false
225
226allOf:
227  - if:
228      properties:
229        compatible:
230          contains:
231            enum:
232              - nvidia,tegra186-smmu
233              - nvidia,tegra194-smmu
234              - nvidia,tegra234-smmu
235    then:
236      properties:
237        reg:
238          minItems: 1
239          maxItems: 2
240
241      # The reference to the memory controller is required to ensure that the
242      # memory client to stream ID mapping can be done synchronously with the
243      # IOMMU attachment.
244      required:
245        - nvidia,memory-controller
246    else:
247      properties:
248        reg:
249          maxItems: 1
250
251  - if:
252      properties:
253        compatible:
254          contains:
255            enum:
256              - qcom,msm8998-smmu-v2
257              - qcom,sdm630-smmu-v2
258    then:
259      anyOf:
260        - properties:
261            clock-names:
262              items:
263                - const: bus
264            clocks:
265              items:
266                - description: bus clock required for downstream bus access and for
267                    the smmu ptw
268        - properties:
269            clock-names:
270              items:
271                - const: iface
272                - const: mem
273                - const: mem_iface
274            clocks:
275              items:
276                - description: interface clock required to access smmu's registers
277                    through the TCU's programming interface.
278                - description: bus clock required for memory access
279                - description: bus clock required for GPU memory access
280        - properties:
281            clock-names:
282              items:
283                - const: iface-mm
284                - const: iface-smmu
285                - const: bus-mm
286                - const: bus-smmu
287            clocks:
288              items:
289                - description: interface clock required to access mnoc's registers
290                    through the TCU's programming interface.
291                - description: interface clock required to access smmu's registers
292                    through the TCU's programming interface.
293                - description: bus clock required for downstream bus access
294                - description: bus clock required for the smmu ptw
295
296  - if:
297      properties:
298        compatible:
299          contains:
300            enum:
301              - qcom,msm8996-smmu-v2
302              - qcom,sc7180-smmu-v2
303              - qcom,sdm845-smmu-v2
304    then:
305      properties:
306        clock-names:
307          items:
308            - const: bus
309            - const: iface
310
311        clocks:
312          items:
313            - description: bus clock required for downstream bus access and for
314                the smmu ptw
315            - description: interface clock required to access smmu's registers
316                through the TCU's programming interface.
317
318  - if:
319      properties:
320        compatible:
321          contains:
322            const: qcom,sc7280-smmu-500
323    then:
324      properties:
325        clock-names:
326          items:
327            - const: gcc_gpu_memnoc_gfx_clk
328            - const: gcc_gpu_snoc_dvm_gfx_clk
329            - const: gpu_cc_ahb_clk
330            - const: gpu_cc_hlos1_vote_gpu_smmu_clk
331            - const: gpu_cc_cx_gmu_clk
332            - const: gpu_cc_hub_cx_int_clk
333            - const: gpu_cc_hub_aon_clk
334
335        clocks:
336          items:
337            - description: GPU memnoc_gfx clock
338            - description: GPU snoc_dvm_gfx clock
339            - description: GPU ahb clock
340            - description: GPU hlos1_vote_GPU smmu clock
341            - description: GPU cx_gmu clock
342            - description: GPU hub_cx_int clock
343            - description: GPU hub_aon clock
344
345  - if:
346      properties:
347        compatible:
348          contains:
349            enum:
350              - qcom,sm6350-smmu-v2
351              - qcom,sm8150-smmu-500
352              - qcom,sm8250-smmu-500
353    then:
354      properties:
355        clock-names:
356          items:
357            - const: ahb
358            - const: bus
359            - const: iface
360
361        clocks:
362          items:
363            - description: bus clock required for AHB bus access
364            - description: bus clock required for downstream bus access and for
365                the smmu ptw
366            - description: interface clock required to access smmu's registers
367                through the TCU's programming interface.
368
369examples:
370  - |+
371    /* SMMU with stream matching or stream indexing */
372    smmu1: iommu@ba5e0000 {
373            compatible = "arm,smmu-v1";
374            reg = <0xba5e0000 0x10000>;
375            #global-interrupts = <2>;
376            interrupts = <0 32 4>,
377                         <0 33 4>,
378                         <0 34 4>, /* This is the first context interrupt */
379                         <0 35 4>,
380                         <0 36 4>,
381                         <0 37 4>;
382            #iommu-cells = <1>;
383    };
384
385    /* device with two stream IDs, 0 and 7 */
386    master1 {
387            iommus = <&smmu1 0>,
388                     <&smmu1 7>;
389    };
390
391
392    /* SMMU with stream matching */
393    smmu2: iommu@ba5f0000 {
394            compatible = "arm,smmu-v1";
395            reg = <0xba5f0000 0x10000>;
396            #global-interrupts = <2>;
397            interrupts = <0 38 4>,
398                         <0 39 4>,
399                         <0 40 4>, /* This is the first context interrupt */
400                         <0 41 4>,
401                         <0 42 4>,
402                         <0 43 4>;
403            #iommu-cells = <2>;
404    };
405
406    /* device with stream IDs 0 and 7 */
407    master2 {
408            iommus = <&smmu2 0 0>,
409                     <&smmu2 7 0>;
410    };
411
412    /* device with stream IDs 1, 17, 33 and 49 */
413    master3 {
414            iommus = <&smmu2 1 0x30>;
415    };
416
417
418    /* ARM MMU-500 with 10-bit stream ID input configuration */
419    smmu3: iommu@ba600000 {
420            compatible = "arm,mmu-500", "arm,smmu-v2";
421            reg = <0xba600000 0x10000>;
422            #global-interrupts = <2>;
423            interrupts = <0 44 4>,
424                         <0 45 4>,
425                         <0 46 4>, /* This is the first context interrupt */
426                         <0 47 4>,
427                         <0 48 4>,
428                         <0 49 4>;
429            #iommu-cells = <1>;
430            /* always ignore appended 5-bit TBU number */
431            stream-match-mask = <0x7c00>;
432    };
433
434    bus {
435            /* bus whose child devices emit one unique 10-bit stream
436               ID each, but may master through multiple SMMU TBUs */
437            iommu-map = <0 &smmu3 0 0x400>;
438
439
440    };
441
442  - |+
443    /* Qcom's arm,smmu-v2 implementation */
444    #include <dt-bindings/interrupt-controller/arm-gic.h>
445    #include <dt-bindings/interrupt-controller/irq.h>
446    smmu4: iommu@d00000 {
447      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
448      reg = <0xd00000 0x10000>;
449
450      #global-interrupts = <1>;
451      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
452             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
453             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
454      #iommu-cells = <1>;
455      power-domains = <&mmcc 0>;
456
457      clocks = <&mmcc 123>,
458        <&mmcc 124>;
459      clock-names = "bus", "iface";
460    };
461