1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31              - qcom,sdm845-smmu-v2
32          - const: qcom,smmu-v2
33
34      - description: Qcom SoCs implementing "arm,mmu-500"
35        items:
36          - enum:
37              - qcom,sc7180-smmu-500
38              - qcom,sdm845-smmu-500
39          - const: arm,mmu-500
40      - items:
41          - const: arm,mmu-500
42          - const: arm,smmu-v2
43      - items:
44          - const: arm,mmu-401
45          - const: arm,smmu-v1
46      - enum:
47          - arm,smmu-v1
48          - arm,smmu-v2
49          - arm,mmu-400
50          - arm,mmu-401
51          - arm,mmu-500
52          - cavium,smmu-v2
53
54  reg:
55    maxItems: 1
56
57  '#global-interrupts':
58    description: The number of global interrupts exposed by the device.
59    $ref: /schemas/types.yaml#/definitions/uint32
60    minimum: 0
61    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
62
63  '#iommu-cells':
64    enum: [ 1, 2 ]
65    description: |
66      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
67      value of 1, each IOMMU specifier represents a distinct stream ID emitted
68      by that device into the relevant SMMU.
69
70      SMMUs with stream matching support and complex masters may use a value of
71      2, where the second cell of the IOMMU specifier represents an SMR mask to
72      combine with the ID in the first cell.  Care must be taken to ensure the
73      set of matched IDs does not result in conflicts.
74
75  interrupts:
76    minItems: 1
77    maxItems: 388   # 260 plus 128 contexts
78    description: |
79      Interrupt list, with the first #global-interrupts entries corresponding to
80      the global interrupts and any following entries corresponding to context
81      interrupts, specified in order of their indexing by the SMMU.
82
83      For SMMUv2 implementations, there must be exactly one interrupt per
84      context bank. In the case of a single, combined interrupt, it must be
85      listed multiple times.
86
87  dma-coherent:
88    description: |
89      Present if page table walks made by the SMMU are cache coherent with the
90      CPU.
91
92      NOTE: this only applies to the SMMU itself, not masters connected
93      upstream of the SMMU.
94
95  calxeda,smmu-secure-config-access:
96    type: boolean
97    description:
98      Enable proper handling of buggy implementations that always use secure
99      access to SMMU configuration registers. In this case non-secure aliases of
100      secure registers have to be used during SMMU configuration.
101
102  stream-match-mask:
103    $ref: /schemas/types.yaml#/definitions/uint32
104    description: |
105      For SMMUs supporting stream matching and using #iommu-cells = <1>,
106      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
107      be programmed into the SMRn.MASK field of every stream match register
108      used). For cases where it is desirable to ignore some portion of every
109      Stream ID (e.g. for certain MMU-500 configurations given globally unique
110      input IDs). This property is not valid for SMMUs using stream indexing, or
111      using stream matching with #iommu-cells = <2>, and may be ignored if
112      present in such cases.
113
114  clock-names:
115    items:
116      - const: bus
117      - const: iface
118
119  clocks:
120    items:
121      - description: bus clock required for downstream bus access and for the
122          smmu ptw
123      - description: interface clock required to access smmu's registers
124          through the TCU's programming interface.
125
126  power-domains:
127    maxItems: 1
128
129required:
130  - compatible
131  - reg
132  - '#global-interrupts'
133  - '#iommu-cells'
134  - interrupts
135
136additionalProperties: false
137
138examples:
139  - |+
140    /* SMMU with stream matching or stream indexing */
141    smmu1: iommu@ba5e0000 {
142            compatible = "arm,smmu-v1";
143            reg = <0xba5e0000 0x10000>;
144            #global-interrupts = <2>;
145            interrupts = <0 32 4>,
146                         <0 33 4>,
147                         <0 34 4>, /* This is the first context interrupt */
148                         <0 35 4>,
149                         <0 36 4>,
150                         <0 37 4>;
151            #iommu-cells = <1>;
152    };
153
154    /* device with two stream IDs, 0 and 7 */
155    master1 {
156            iommus = <&smmu1 0>,
157                     <&smmu1 7>;
158    };
159
160
161    /* SMMU with stream matching */
162    smmu2: iommu@ba5f0000 {
163            compatible = "arm,smmu-v1";
164            reg = <0xba5f0000 0x10000>;
165            #global-interrupts = <2>;
166            interrupts = <0 38 4>,
167                         <0 39 4>,
168                         <0 40 4>, /* This is the first context interrupt */
169                         <0 41 4>,
170                         <0 42 4>,
171                         <0 43 4>;
172            #iommu-cells = <2>;
173    };
174
175    /* device with stream IDs 0 and 7 */
176    master2 {
177            iommus = <&smmu2 0 0>,
178                     <&smmu2 7 0>;
179    };
180
181    /* device with stream IDs 1, 17, 33 and 49 */
182    master3 {
183            iommus = <&smmu2 1 0x30>;
184    };
185
186
187    /* ARM MMU-500 with 10-bit stream ID input configuration */
188    smmu3: iommu@ba600000 {
189            compatible = "arm,mmu-500", "arm,smmu-v2";
190            reg = <0xba600000 0x10000>;
191            #global-interrupts = <2>;
192            interrupts = <0 44 4>,
193                         <0 45 4>,
194                         <0 46 4>, /* This is the first context interrupt */
195                         <0 47 4>,
196                         <0 48 4>,
197                         <0 49 4>;
198            #iommu-cells = <1>;
199            /* always ignore appended 5-bit TBU number */
200            stream-match-mask = <0x7c00>;
201    };
202
203    bus {
204            /* bus whose child devices emit one unique 10-bit stream
205               ID each, but may master through multiple SMMU TBUs */
206            iommu-map = <0 &smmu3 0 0x400>;
207
208
209    };
210
211  - |+
212    /* Qcom's arm,smmu-v2 implementation */
213    #include <dt-bindings/interrupt-controller/arm-gic.h>
214    #include <dt-bindings/interrupt-controller/irq.h>
215    smmu4: iommu@d00000 {
216      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
217      reg = <0xd00000 0x10000>;
218
219      #global-interrupts = <1>;
220      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
221             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
222             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
223      #iommu-cells = <1>;
224      power-domains = <&mmcc 0>;
225
226      clocks = <&mmcc 123>,
227        <&mmcc 124>;
228      clock-names = "bus", "iface";
229    };
230