1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31          - const: qcom,smmu-v2
32
33      - description: Qcom SoCs implementing "arm,mmu-500"
34        items:
35          - enum:
36              - qcom,sc7180-smmu-500
37              - qcom,sc7280-smmu-500
38              - qcom,sc8180x-smmu-500
39              - qcom,sdm845-smmu-500
40              - qcom,sm8150-smmu-500
41              - qcom,sm8250-smmu-500
42              - qcom,sm8350-smmu-500
43          - const: arm,mmu-500
44      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
45        items:
46          - enum:
47              - qcom,sc7180-smmu-v2
48              - qcom,sdm845-smmu-v2
49          - const: qcom,adreno-smmu
50          - const: qcom,smmu-v2
51      - description: Marvell SoCs implementing "arm,mmu-500"
52        items:
53          - const: marvell,ap806-smmu-500
54          - const: arm,mmu-500
55      - description: NVIDIA SoCs that program two ARM MMU-500s identically
56        items:
57      - description: NVIDIA SoCs that require memory controller interaction
58          and may program multiple ARM MMU-500s identically with the memory
59          controller interleaving translations between multiple instances
60          for improved performance.
61        items:
62          - enum:
63              - const: nvidia,tegra194-smmu
64              - const: nvidia,tegra186-smmu
65          - const: nvidia,smmu-500
66      - items:
67          - const: arm,mmu-500
68          - const: arm,smmu-v2
69      - items:
70          - enum:
71              - arm,mmu-400
72              - arm,mmu-401
73          - const: arm,smmu-v1
74      - enum:
75          - arm,smmu-v1
76          - arm,smmu-v2
77          - arm,mmu-400
78          - arm,mmu-401
79          - arm,mmu-500
80          - cavium,smmu-v2
81
82  reg:
83    minItems: 1
84    maxItems: 2
85
86  '#global-interrupts':
87    description: The number of global interrupts exposed by the device.
88    $ref: /schemas/types.yaml#/definitions/uint32
89    minimum: 0
90    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
91
92  '#iommu-cells':
93    enum: [ 1, 2 ]
94    description: |
95      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
96      value of 1, each IOMMU specifier represents a distinct stream ID emitted
97      by that device into the relevant SMMU.
98
99      SMMUs with stream matching support and complex masters may use a value of
100      2, where the second cell of the IOMMU specifier represents an SMR mask to
101      combine with the ID in the first cell.  Care must be taken to ensure the
102      set of matched IDs does not result in conflicts.
103
104  interrupts:
105    minItems: 1
106    maxItems: 388   # 260 plus 128 contexts
107    description: |
108      Interrupt list, with the first #global-interrupts entries corresponding to
109      the global interrupts and any following entries corresponding to context
110      interrupts, specified in order of their indexing by the SMMU.
111
112      For SMMUv2 implementations, there must be exactly one interrupt per
113      context bank. In the case of a single, combined interrupt, it must be
114      listed multiple times.
115
116  dma-coherent:
117    description: |
118      Present if page table walks made by the SMMU are cache coherent with the
119      CPU.
120
121      NOTE: this only applies to the SMMU itself, not masters connected
122      upstream of the SMMU.
123
124  calxeda,smmu-secure-config-access:
125    type: boolean
126    description:
127      Enable proper handling of buggy implementations that always use secure
128      access to SMMU configuration registers. In this case non-secure aliases of
129      secure registers have to be used during SMMU configuration.
130
131  stream-match-mask:
132    $ref: /schemas/types.yaml#/definitions/uint32
133    description: |
134      For SMMUs supporting stream matching and using #iommu-cells = <1>,
135      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
136      be programmed into the SMRn.MASK field of every stream match register
137      used). For cases where it is desirable to ignore some portion of every
138      Stream ID (e.g. for certain MMU-500 configurations given globally unique
139      input IDs). This property is not valid for SMMUs using stream indexing, or
140      using stream matching with #iommu-cells = <2>, and may be ignored if
141      present in such cases.
142
143  clock-names:
144    items:
145      - const: bus
146      - const: iface
147
148  clocks:
149    items:
150      - description: bus clock required for downstream bus access and for the
151          smmu ptw
152      - description: interface clock required to access smmu's registers
153          through the TCU's programming interface.
154
155  power-domains:
156    maxItems: 1
157
158required:
159  - compatible
160  - reg
161  - '#global-interrupts'
162  - '#iommu-cells'
163  - interrupts
164
165additionalProperties: false
166
167allOf:
168  - if:
169      properties:
170        compatible:
171          contains:
172            enum:
173              - nvidia,tegra194-smmu
174              - nvidia,tegra186-smmu
175    then:
176      properties:
177        reg:
178          minItems: 1
179          maxItems: 2
180    else:
181      properties:
182        reg:
183          maxItems: 1
184
185examples:
186  - |+
187    /* SMMU with stream matching or stream indexing */
188    smmu1: iommu@ba5e0000 {
189            compatible = "arm,smmu-v1";
190            reg = <0xba5e0000 0x10000>;
191            #global-interrupts = <2>;
192            interrupts = <0 32 4>,
193                         <0 33 4>,
194                         <0 34 4>, /* This is the first context interrupt */
195                         <0 35 4>,
196                         <0 36 4>,
197                         <0 37 4>;
198            #iommu-cells = <1>;
199    };
200
201    /* device with two stream IDs, 0 and 7 */
202    master1 {
203            iommus = <&smmu1 0>,
204                     <&smmu1 7>;
205    };
206
207
208    /* SMMU with stream matching */
209    smmu2: iommu@ba5f0000 {
210            compatible = "arm,smmu-v1";
211            reg = <0xba5f0000 0x10000>;
212            #global-interrupts = <2>;
213            interrupts = <0 38 4>,
214                         <0 39 4>,
215                         <0 40 4>, /* This is the first context interrupt */
216                         <0 41 4>,
217                         <0 42 4>,
218                         <0 43 4>;
219            #iommu-cells = <2>;
220    };
221
222    /* device with stream IDs 0 and 7 */
223    master2 {
224            iommus = <&smmu2 0 0>,
225                     <&smmu2 7 0>;
226    };
227
228    /* device with stream IDs 1, 17, 33 and 49 */
229    master3 {
230            iommus = <&smmu2 1 0x30>;
231    };
232
233
234    /* ARM MMU-500 with 10-bit stream ID input configuration */
235    smmu3: iommu@ba600000 {
236            compatible = "arm,mmu-500", "arm,smmu-v2";
237            reg = <0xba600000 0x10000>;
238            #global-interrupts = <2>;
239            interrupts = <0 44 4>,
240                         <0 45 4>,
241                         <0 46 4>, /* This is the first context interrupt */
242                         <0 47 4>,
243                         <0 48 4>,
244                         <0 49 4>;
245            #iommu-cells = <1>;
246            /* always ignore appended 5-bit TBU number */
247            stream-match-mask = <0x7c00>;
248    };
249
250    bus {
251            /* bus whose child devices emit one unique 10-bit stream
252               ID each, but may master through multiple SMMU TBUs */
253            iommu-map = <0 &smmu3 0 0x400>;
254
255
256    };
257
258  - |+
259    /* Qcom's arm,smmu-v2 implementation */
260    #include <dt-bindings/interrupt-controller/arm-gic.h>
261    #include <dt-bindings/interrupt-controller/irq.h>
262    smmu4: iommu@d00000 {
263      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
264      reg = <0xd00000 0x10000>;
265
266      #global-interrupts = <1>;
267      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
268             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
269             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
270      #iommu-cells = <1>;
271      power-domains = <&mmcc 0>;
272
273      clocks = <&mmcc 123>,
274        <&mmcc 124>;
275      clock-names = "bus", "iface";
276    };
277