1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31          - const: qcom,smmu-v2
32
33      - description: Qcom SoCs implementing "arm,mmu-500"
34        items:
35          - enum:
36              - qcom,qcm2290-smmu-500
37              - qcom,sc7180-smmu-500
38              - qcom,sc7280-smmu-500
39              - qcom,sc8180x-smmu-500
40              - qcom,sc8280xp-smmu-500
41              - qcom,sdm845-smmu-500
42              - qcom,sdx55-smmu-500
43              - qcom,sdx65-smmu-500
44              - qcom,sm6350-smmu-500
45              - qcom,sm6375-smmu-500
46              - qcom,sm8150-smmu-500
47              - qcom,sm8250-smmu-500
48              - qcom,sm8350-smmu-500
49              - qcom,sm8450-smmu-500
50          - const: arm,mmu-500
51      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
52        items:
53          - enum:
54              - qcom,sc7180-smmu-v2
55              - qcom,sdm845-smmu-v2
56          - const: qcom,adreno-smmu
57          - const: qcom,smmu-v2
58      - description: Marvell SoCs implementing "arm,mmu-500"
59        items:
60          - const: marvell,ap806-smmu-500
61          - const: arm,mmu-500
62      - description: NVIDIA SoCs that require memory controller interaction
63          and may program multiple ARM MMU-500s identically with the memory
64          controller interleaving translations between multiple instances
65          for improved performance.
66        items:
67          - enum:
68              - nvidia,tegra186-smmu
69              - nvidia,tegra194-smmu
70              - nvidia,tegra234-smmu
71          - const: nvidia,smmu-500
72      - items:
73          - const: arm,mmu-500
74          - const: arm,smmu-v2
75      - items:
76          - enum:
77              - arm,mmu-400
78              - arm,mmu-401
79          - const: arm,smmu-v1
80      - enum:
81          - arm,smmu-v1
82          - arm,smmu-v2
83          - arm,mmu-400
84          - arm,mmu-401
85          - arm,mmu-500
86          - cavium,smmu-v2
87
88  reg:
89    minItems: 1
90    maxItems: 2
91
92  '#global-interrupts':
93    description: The number of global interrupts exposed by the device.
94    $ref: /schemas/types.yaml#/definitions/uint32
95    minimum: 0
96    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
97
98  '#iommu-cells':
99    enum: [ 1, 2 ]
100    description: |
101      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
102      value of 1, each IOMMU specifier represents a distinct stream ID emitted
103      by that device into the relevant SMMU.
104
105      SMMUs with stream matching support and complex masters may use a value of
106      2, where the second cell of the IOMMU specifier represents an SMR mask to
107      combine with the ID in the first cell.  Care must be taken to ensure the
108      set of matched IDs does not result in conflicts.
109
110  interrupts:
111    minItems: 1
112    maxItems: 388   # 260 plus 128 contexts
113    description: |
114      Interrupt list, with the first #global-interrupts entries corresponding to
115      the global interrupts and any following entries corresponding to context
116      interrupts, specified in order of their indexing by the SMMU.
117
118      For SMMUv2 implementations, there must be exactly one interrupt per
119      context bank. In the case of a single, combined interrupt, it must be
120      listed multiple times.
121
122  dma-coherent:
123    description: |
124      Present if page table walks made by the SMMU are cache coherent with the
125      CPU.
126
127      NOTE: this only applies to the SMMU itself, not masters connected
128      upstream of the SMMU.
129
130  calxeda,smmu-secure-config-access:
131    type: boolean
132    description:
133      Enable proper handling of buggy implementations that always use secure
134      access to SMMU configuration registers. In this case non-secure aliases of
135      secure registers have to be used during SMMU configuration.
136
137  stream-match-mask:
138    $ref: /schemas/types.yaml#/definitions/uint32
139    description: |
140      For SMMUs supporting stream matching and using #iommu-cells = <1>,
141      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
142      be programmed into the SMRn.MASK field of every stream match register
143      used). For cases where it is desirable to ignore some portion of every
144      Stream ID (e.g. for certain MMU-500 configurations given globally unique
145      input IDs). This property is not valid for SMMUs using stream indexing, or
146      using stream matching with #iommu-cells = <2>, and may be ignored if
147      present in such cases.
148
149  clock-names:
150    items:
151      - const: bus
152      - const: iface
153
154  clocks:
155    items:
156      - description: bus clock required for downstream bus access and for the
157          smmu ptw
158      - description: interface clock required to access smmu's registers
159          through the TCU's programming interface.
160
161  power-domains:
162    maxItems: 1
163
164  nvidia,memory-controller:
165    description: |
166      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
167      The memory controller needs to be programmed with a mapping of memory
168      client IDs to ARM SMMU stream IDs.
169
170      If this property is absent, the mapping programmed by early firmware
171      will be used and it is not guaranteed that IOMMU translations will be
172      enabled for any given device.
173    $ref: /schemas/types.yaml#/definitions/phandle
174
175required:
176  - compatible
177  - reg
178  - '#global-interrupts'
179  - '#iommu-cells'
180  - interrupts
181
182additionalProperties: false
183
184allOf:
185  - if:
186      properties:
187        compatible:
188          contains:
189            enum:
190              - nvidia,tegra186-smmu
191              - nvidia,tegra194-smmu
192              - nvidia,tegra234-smmu
193    then:
194      properties:
195        reg:
196          minItems: 1
197          maxItems: 2
198
199      # The reference to the memory controller is required to ensure that the
200      # memory client to stream ID mapping can be done synchronously with the
201      # IOMMU attachment.
202      required:
203        - nvidia,memory-controller
204    else:
205      properties:
206        reg:
207          maxItems: 1
208
209examples:
210  - |+
211    /* SMMU with stream matching or stream indexing */
212    smmu1: iommu@ba5e0000 {
213            compatible = "arm,smmu-v1";
214            reg = <0xba5e0000 0x10000>;
215            #global-interrupts = <2>;
216            interrupts = <0 32 4>,
217                         <0 33 4>,
218                         <0 34 4>, /* This is the first context interrupt */
219                         <0 35 4>,
220                         <0 36 4>,
221                         <0 37 4>;
222            #iommu-cells = <1>;
223    };
224
225    /* device with two stream IDs, 0 and 7 */
226    master1 {
227            iommus = <&smmu1 0>,
228                     <&smmu1 7>;
229    };
230
231
232    /* SMMU with stream matching */
233    smmu2: iommu@ba5f0000 {
234            compatible = "arm,smmu-v1";
235            reg = <0xba5f0000 0x10000>;
236            #global-interrupts = <2>;
237            interrupts = <0 38 4>,
238                         <0 39 4>,
239                         <0 40 4>, /* This is the first context interrupt */
240                         <0 41 4>,
241                         <0 42 4>,
242                         <0 43 4>;
243            #iommu-cells = <2>;
244    };
245
246    /* device with stream IDs 0 and 7 */
247    master2 {
248            iommus = <&smmu2 0 0>,
249                     <&smmu2 7 0>;
250    };
251
252    /* device with stream IDs 1, 17, 33 and 49 */
253    master3 {
254            iommus = <&smmu2 1 0x30>;
255    };
256
257
258    /* ARM MMU-500 with 10-bit stream ID input configuration */
259    smmu3: iommu@ba600000 {
260            compatible = "arm,mmu-500", "arm,smmu-v2";
261            reg = <0xba600000 0x10000>;
262            #global-interrupts = <2>;
263            interrupts = <0 44 4>,
264                         <0 45 4>,
265                         <0 46 4>, /* This is the first context interrupt */
266                         <0 47 4>,
267                         <0 48 4>,
268                         <0 49 4>;
269            #iommu-cells = <1>;
270            /* always ignore appended 5-bit TBU number */
271            stream-match-mask = <0x7c00>;
272    };
273
274    bus {
275            /* bus whose child devices emit one unique 10-bit stream
276               ID each, but may master through multiple SMMU TBUs */
277            iommu-map = <0 &smmu3 0 0x400>;
278
279
280    };
281
282  - |+
283    /* Qcom's arm,smmu-v2 implementation */
284    #include <dt-bindings/interrupt-controller/arm-gic.h>
285    #include <dt-bindings/interrupt-controller/irq.h>
286    smmu4: iommu@d00000 {
287      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
288      reg = <0xd00000 0x10000>;
289
290      #global-interrupts = <1>;
291      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
292             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
293             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
294      #iommu-cells = <1>;
295      power-domains = <&mmcc 0>;
296
297      clocks = <&mmcc 123>,
298        <&mmcc 124>;
299      clock-names = "bus", "iface";
300    };
301