1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31          - const: qcom,smmu-v2
32
33      - description: Qcom SoCs implementing "arm,mmu-500"
34        items:
35          - enum:
36              - qcom,sc7180-smmu-500
37              - qcom,sdm845-smmu-500
38              - qcom,sm8150-smmu-500
39              - qcom,sm8250-smmu-500
40          - const: arm,mmu-500
41      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
42        items:
43          - enum:
44              - qcom,sc7180-smmu-v2
45              - qcom,sdm845-smmu-v2
46          - const: qcom,adreno-smmu
47          - const: qcom,smmu-v2
48      - description: Marvell SoCs implementing "arm,mmu-500"
49        items:
50          - const: marvell,ap806-smmu-500
51          - const: arm,mmu-500
52      - description: NVIDIA SoCs that program two ARM MMU-500s identically
53        items:
54          - enum:
55              - nvidia,tegra194-smmu
56          - const: nvidia,smmu-500
57      - items:
58          - const: arm,mmu-500
59          - const: arm,smmu-v2
60      - items:
61          - enum:
62              - arm,mmu-400
63              - arm,mmu-401
64          - const: arm,smmu-v1
65      - enum:
66          - arm,smmu-v1
67          - arm,smmu-v2
68          - arm,mmu-400
69          - arm,mmu-401
70          - arm,mmu-500
71          - cavium,smmu-v2
72
73  reg:
74    minItems: 1
75    maxItems: 2
76
77  '#global-interrupts':
78    description: The number of global interrupts exposed by the device.
79    $ref: /schemas/types.yaml#/definitions/uint32
80    minimum: 0
81    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
82
83  '#iommu-cells':
84    enum: [ 1, 2 ]
85    description: |
86      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
87      value of 1, each IOMMU specifier represents a distinct stream ID emitted
88      by that device into the relevant SMMU.
89
90      SMMUs with stream matching support and complex masters may use a value of
91      2, where the second cell of the IOMMU specifier represents an SMR mask to
92      combine with the ID in the first cell.  Care must be taken to ensure the
93      set of matched IDs does not result in conflicts.
94
95  interrupts:
96    minItems: 1
97    maxItems: 388   # 260 plus 128 contexts
98    description: |
99      Interrupt list, with the first #global-interrupts entries corresponding to
100      the global interrupts and any following entries corresponding to context
101      interrupts, specified in order of their indexing by the SMMU.
102
103      For SMMUv2 implementations, there must be exactly one interrupt per
104      context bank. In the case of a single, combined interrupt, it must be
105      listed multiple times.
106
107  dma-coherent:
108    description: |
109      Present if page table walks made by the SMMU are cache coherent with the
110      CPU.
111
112      NOTE: this only applies to the SMMU itself, not masters connected
113      upstream of the SMMU.
114
115  calxeda,smmu-secure-config-access:
116    type: boolean
117    description:
118      Enable proper handling of buggy implementations that always use secure
119      access to SMMU configuration registers. In this case non-secure aliases of
120      secure registers have to be used during SMMU configuration.
121
122  stream-match-mask:
123    $ref: /schemas/types.yaml#/definitions/uint32
124    description: |
125      For SMMUs supporting stream matching and using #iommu-cells = <1>,
126      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
127      be programmed into the SMRn.MASK field of every stream match register
128      used). For cases where it is desirable to ignore some portion of every
129      Stream ID (e.g. for certain MMU-500 configurations given globally unique
130      input IDs). This property is not valid for SMMUs using stream indexing, or
131      using stream matching with #iommu-cells = <2>, and may be ignored if
132      present in such cases.
133
134  clock-names:
135    items:
136      - const: bus
137      - const: iface
138
139  clocks:
140    items:
141      - description: bus clock required for downstream bus access and for the
142          smmu ptw
143      - description: interface clock required to access smmu's registers
144          through the TCU's programming interface.
145
146  power-domains:
147    maxItems: 1
148
149required:
150  - compatible
151  - reg
152  - '#global-interrupts'
153  - '#iommu-cells'
154  - interrupts
155
156additionalProperties: false
157
158allOf:
159  - if:
160      properties:
161        compatible:
162          contains:
163            enum:
164              - nvidia,tegra194-smmu
165    then:
166      properties:
167        reg:
168          minItems: 2
169          maxItems: 2
170    else:
171      properties:
172        reg:
173          maxItems: 1
174
175examples:
176  - |+
177    /* SMMU with stream matching or stream indexing */
178    smmu1: iommu@ba5e0000 {
179            compatible = "arm,smmu-v1";
180            reg = <0xba5e0000 0x10000>;
181            #global-interrupts = <2>;
182            interrupts = <0 32 4>,
183                         <0 33 4>,
184                         <0 34 4>, /* This is the first context interrupt */
185                         <0 35 4>,
186                         <0 36 4>,
187                         <0 37 4>;
188            #iommu-cells = <1>;
189    };
190
191    /* device with two stream IDs, 0 and 7 */
192    master1 {
193            iommus = <&smmu1 0>,
194                     <&smmu1 7>;
195    };
196
197
198    /* SMMU with stream matching */
199    smmu2: iommu@ba5f0000 {
200            compatible = "arm,smmu-v1";
201            reg = <0xba5f0000 0x10000>;
202            #global-interrupts = <2>;
203            interrupts = <0 38 4>,
204                         <0 39 4>,
205                         <0 40 4>, /* This is the first context interrupt */
206                         <0 41 4>,
207                         <0 42 4>,
208                         <0 43 4>;
209            #iommu-cells = <2>;
210    };
211
212    /* device with stream IDs 0 and 7 */
213    master2 {
214            iommus = <&smmu2 0 0>,
215                     <&smmu2 7 0>;
216    };
217
218    /* device with stream IDs 1, 17, 33 and 49 */
219    master3 {
220            iommus = <&smmu2 1 0x30>;
221    };
222
223
224    /* ARM MMU-500 with 10-bit stream ID input configuration */
225    smmu3: iommu@ba600000 {
226            compatible = "arm,mmu-500", "arm,smmu-v2";
227            reg = <0xba600000 0x10000>;
228            #global-interrupts = <2>;
229            interrupts = <0 44 4>,
230                         <0 45 4>,
231                         <0 46 4>, /* This is the first context interrupt */
232                         <0 47 4>,
233                         <0 48 4>,
234                         <0 49 4>;
235            #iommu-cells = <1>;
236            /* always ignore appended 5-bit TBU number */
237            stream-match-mask = <0x7c00>;
238    };
239
240    bus {
241            /* bus whose child devices emit one unique 10-bit stream
242               ID each, but may master through multiple SMMU TBUs */
243            iommu-map = <0 &smmu3 0 0x400>;
244
245
246    };
247
248  - |+
249    /* Qcom's arm,smmu-v2 implementation */
250    #include <dt-bindings/interrupt-controller/arm-gic.h>
251    #include <dt-bindings/interrupt-controller/irq.h>
252    smmu4: iommu@d00000 {
253      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
254      reg = <0xd00000 0x10000>;
255
256      #global-interrupts = <1>;
257      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
258             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
259             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
260      #iommu-cells = <1>;
261      power-domains = <&mmcc 0>;
262
263      clocks = <&mmcc 123>,
264        <&mmcc 124>;
265      clock-names = "bus", "iface";
266    };
267