1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM System MMU Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  ARM SoCs may contain an implementation of the ARM System Memory
15  Management Unit Architecture, which can be used to provide 1 or 2 stages
16  of address translation to bus masters external to the CPU.
17
18  The SMMU may also raise interrupts in response to various fault
19  conditions.
20
21properties:
22  $nodename:
23    pattern: "^iommu@[0-9a-f]*"
24  compatible:
25    oneOf:
26      - description: Qcom SoCs implementing "arm,smmu-v2"
27        items:
28          - enum:
29              - qcom,msm8996-smmu-v2
30              - qcom,msm8998-smmu-v2
31          - const: qcom,smmu-v2
32
33      - description: Qcom SoCs implementing "arm,mmu-500"
34        items:
35          - enum:
36              - qcom,sc7180-smmu-500
37              - qcom,sc8180x-smmu-500
38              - qcom,sdm845-smmu-500
39              - qcom,sm8150-smmu-500
40              - qcom,sm8250-smmu-500
41              - qcom,sm8350-smmu-500
42          - const: arm,mmu-500
43      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
44        items:
45          - enum:
46              - qcom,sc7180-smmu-v2
47              - qcom,sdm845-smmu-v2
48          - const: qcom,adreno-smmu
49          - const: qcom,smmu-v2
50      - description: Marvell SoCs implementing "arm,mmu-500"
51        items:
52          - const: marvell,ap806-smmu-500
53          - const: arm,mmu-500
54      - description: NVIDIA SoCs that program two ARM MMU-500s identically
55        items:
56          - enum:
57              - nvidia,tegra194-smmu
58          - const: nvidia,smmu-500
59      - items:
60          - const: arm,mmu-500
61          - const: arm,smmu-v2
62      - items:
63          - enum:
64              - arm,mmu-400
65              - arm,mmu-401
66          - const: arm,smmu-v1
67      - enum:
68          - arm,smmu-v1
69          - arm,smmu-v2
70          - arm,mmu-400
71          - arm,mmu-401
72          - arm,mmu-500
73          - cavium,smmu-v2
74
75  reg:
76    minItems: 1
77    maxItems: 2
78
79  '#global-interrupts':
80    description: The number of global interrupts exposed by the device.
81    $ref: /schemas/types.yaml#/definitions/uint32
82    minimum: 0
83    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters
84
85  '#iommu-cells':
86    enum: [ 1, 2 ]
87    description: |
88      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
89      value of 1, each IOMMU specifier represents a distinct stream ID emitted
90      by that device into the relevant SMMU.
91
92      SMMUs with stream matching support and complex masters may use a value of
93      2, where the second cell of the IOMMU specifier represents an SMR mask to
94      combine with the ID in the first cell.  Care must be taken to ensure the
95      set of matched IDs does not result in conflicts.
96
97  interrupts:
98    minItems: 1
99    maxItems: 388   # 260 plus 128 contexts
100    description: |
101      Interrupt list, with the first #global-interrupts entries corresponding to
102      the global interrupts and any following entries corresponding to context
103      interrupts, specified in order of their indexing by the SMMU.
104
105      For SMMUv2 implementations, there must be exactly one interrupt per
106      context bank. In the case of a single, combined interrupt, it must be
107      listed multiple times.
108
109  dma-coherent:
110    description: |
111      Present if page table walks made by the SMMU are cache coherent with the
112      CPU.
113
114      NOTE: this only applies to the SMMU itself, not masters connected
115      upstream of the SMMU.
116
117  calxeda,smmu-secure-config-access:
118    type: boolean
119    description:
120      Enable proper handling of buggy implementations that always use secure
121      access to SMMU configuration registers. In this case non-secure aliases of
122      secure registers have to be used during SMMU configuration.
123
124  stream-match-mask:
125    $ref: /schemas/types.yaml#/definitions/uint32
126    description: |
127      For SMMUs supporting stream matching and using #iommu-cells = <1>,
128      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
129      be programmed into the SMRn.MASK field of every stream match register
130      used). For cases where it is desirable to ignore some portion of every
131      Stream ID (e.g. for certain MMU-500 configurations given globally unique
132      input IDs). This property is not valid for SMMUs using stream indexing, or
133      using stream matching with #iommu-cells = <2>, and may be ignored if
134      present in such cases.
135
136  clock-names:
137    items:
138      - const: bus
139      - const: iface
140
141  clocks:
142    items:
143      - description: bus clock required for downstream bus access and for the
144          smmu ptw
145      - description: interface clock required to access smmu's registers
146          through the TCU's programming interface.
147
148  power-domains:
149    maxItems: 1
150
151required:
152  - compatible
153  - reg
154  - '#global-interrupts'
155  - '#iommu-cells'
156  - interrupts
157
158additionalProperties: false
159
160allOf:
161  - if:
162      properties:
163        compatible:
164          contains:
165            enum:
166              - nvidia,tegra194-smmu
167    then:
168      properties:
169        reg:
170          minItems: 2
171          maxItems: 2
172    else:
173      properties:
174        reg:
175          maxItems: 1
176
177examples:
178  - |+
179    /* SMMU with stream matching or stream indexing */
180    smmu1: iommu@ba5e0000 {
181            compatible = "arm,smmu-v1";
182            reg = <0xba5e0000 0x10000>;
183            #global-interrupts = <2>;
184            interrupts = <0 32 4>,
185                         <0 33 4>,
186                         <0 34 4>, /* This is the first context interrupt */
187                         <0 35 4>,
188                         <0 36 4>,
189                         <0 37 4>;
190            #iommu-cells = <1>;
191    };
192
193    /* device with two stream IDs, 0 and 7 */
194    master1 {
195            iommus = <&smmu1 0>,
196                     <&smmu1 7>;
197    };
198
199
200    /* SMMU with stream matching */
201    smmu2: iommu@ba5f0000 {
202            compatible = "arm,smmu-v1";
203            reg = <0xba5f0000 0x10000>;
204            #global-interrupts = <2>;
205            interrupts = <0 38 4>,
206                         <0 39 4>,
207                         <0 40 4>, /* This is the first context interrupt */
208                         <0 41 4>,
209                         <0 42 4>,
210                         <0 43 4>;
211            #iommu-cells = <2>;
212    };
213
214    /* device with stream IDs 0 and 7 */
215    master2 {
216            iommus = <&smmu2 0 0>,
217                     <&smmu2 7 0>;
218    };
219
220    /* device with stream IDs 1, 17, 33 and 49 */
221    master3 {
222            iommus = <&smmu2 1 0x30>;
223    };
224
225
226    /* ARM MMU-500 with 10-bit stream ID input configuration */
227    smmu3: iommu@ba600000 {
228            compatible = "arm,mmu-500", "arm,smmu-v2";
229            reg = <0xba600000 0x10000>;
230            #global-interrupts = <2>;
231            interrupts = <0 44 4>,
232                         <0 45 4>,
233                         <0 46 4>, /* This is the first context interrupt */
234                         <0 47 4>,
235                         <0 48 4>,
236                         <0 49 4>;
237            #iommu-cells = <1>;
238            /* always ignore appended 5-bit TBU number */
239            stream-match-mask = <0x7c00>;
240    };
241
242    bus {
243            /* bus whose child devices emit one unique 10-bit stream
244               ID each, but may master through multiple SMMU TBUs */
245            iommu-map = <0 &smmu3 0 0x400>;
246
247
248    };
249
250  - |+
251    /* Qcom's arm,smmu-v2 implementation */
252    #include <dt-bindings/interrupt-controller/arm-gic.h>
253    #include <dt-bindings/interrupt-controller/irq.h>
254    smmu4: iommu@d00000 {
255      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
256      reg = <0xd00000 0x10000>;
257
258      #global-interrupts = <1>;
259      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
260             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
261             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
262      #iommu-cells = <1>;
263      power-domains = <&mmcc 0>;
264
265      clocks = <&mmcc 123>,
266        <&mmcc 124>;
267      clock-names = "bus", "iface";
268    };
269