1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,qcm2290-smmu-500 39 - qcom,qdu1000-smmu-500 40 - qcom,sa8775p-smmu-500 41 - qcom,sc7180-smmu-500 42 - qcom,sc7280-smmu-500 43 - qcom,sc8180x-smmu-500 44 - qcom,sc8280xp-smmu-500 45 - qcom,sdm670-smmu-500 46 - qcom,sdm845-smmu-500 47 - qcom,sdx55-smmu-500 48 - qcom,sdx65-smmu-500 49 - qcom,sdx75-smmu-500 50 - qcom,sm6115-smmu-500 51 - qcom,sm6125-smmu-500 52 - qcom,sm6350-smmu-500 53 - qcom,sm6375-smmu-500 54 - qcom,sm8150-smmu-500 55 - qcom,sm8250-smmu-500 56 - qcom,sm8350-smmu-500 57 - qcom,sm8450-smmu-500 58 - qcom,sm8550-smmu-500 59 - const: qcom,smmu-500 60 - const: arm,mmu-500 61 62 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 63 deprecated: true 64 items: 65 # Do not add additional SoC to this list. Instead use two previous lists. 66 - enum: 67 - qcom,qcm2290-smmu-500 68 - qcom,sc7180-smmu-500 69 - qcom,sc7280-smmu-500 70 - qcom,sc8180x-smmu-500 71 - qcom,sc8280xp-smmu-500 72 - qcom,sdm845-smmu-500 73 - qcom,sm6115-smmu-500 74 - qcom,sm6350-smmu-500 75 - qcom,sm6375-smmu-500 76 - qcom,sm8150-smmu-500 77 - qcom,sm8250-smmu-500 78 - qcom,sm8350-smmu-500 79 - qcom,sm8450-smmu-500 80 - const: arm,mmu-500 81 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 82 items: 83 - enum: 84 - qcom,sa8775p-smmu-500 85 - qcom,sc7280-smmu-500 86 - qcom,sc8280xp-smmu-500 87 - qcom,sm6115-smmu-500 88 - qcom,sm6125-smmu-500 89 - qcom,sm8150-smmu-500 90 - qcom,sm8250-smmu-500 91 - qcom,sm8350-smmu-500 92 - const: qcom,adreno-smmu 93 - const: qcom,smmu-500 94 - const: arm,mmu-500 95 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 96 deprecated: true 97 items: 98 # Do not add additional SoC to this list. Instead use previous list. 99 - enum: 100 - qcom,sc7280-smmu-500 101 - qcom,sm8150-smmu-500 102 - qcom,sm8250-smmu-500 103 - const: qcom,adreno-smmu 104 - const: arm,mmu-500 105 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 106 items: 107 - enum: 108 - qcom,msm8996-smmu-v2 109 - qcom,sc7180-smmu-v2 110 - qcom,sdm630-smmu-v2 111 - qcom,sdm845-smmu-v2 112 - qcom,sm6350-smmu-v2 113 - const: qcom,adreno-smmu 114 - const: qcom,smmu-v2 115 - description: Qcom Adreno GPUs on Google Cheza platform 116 items: 117 - const: qcom,sdm845-smmu-v2 118 - const: qcom,smmu-v2 119 - description: Marvell SoCs implementing "arm,mmu-500" 120 items: 121 - const: marvell,ap806-smmu-500 122 - const: arm,mmu-500 123 - description: NVIDIA SoCs that require memory controller interaction 124 and may program multiple ARM MMU-500s identically with the memory 125 controller interleaving translations between multiple instances 126 for improved performance. 127 items: 128 - enum: 129 - nvidia,tegra186-smmu 130 - nvidia,tegra194-smmu 131 - nvidia,tegra234-smmu 132 - const: nvidia,smmu-500 133 - items: 134 - const: arm,mmu-500 135 - const: arm,smmu-v2 136 - items: 137 - enum: 138 - arm,mmu-400 139 - arm,mmu-401 140 - const: arm,smmu-v1 141 - enum: 142 - arm,smmu-v1 143 - arm,smmu-v2 144 - arm,mmu-400 145 - arm,mmu-401 146 - arm,mmu-500 147 - cavium,smmu-v2 148 149 reg: 150 minItems: 1 151 maxItems: 2 152 153 '#global-interrupts': 154 description: The number of global interrupts exposed by the device. 155 $ref: /schemas/types.yaml#/definitions/uint32 156 minimum: 0 157 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 158 159 '#iommu-cells': 160 enum: [ 1, 2 ] 161 description: | 162 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 163 value of 1, each IOMMU specifier represents a distinct stream ID emitted 164 by that device into the relevant SMMU. 165 166 SMMUs with stream matching support and complex masters may use a value of 167 2, where the second cell of the IOMMU specifier represents an SMR mask to 168 combine with the ID in the first cell. Care must be taken to ensure the 169 set of matched IDs does not result in conflicts. 170 171 interrupts: 172 minItems: 1 173 maxItems: 388 # 260 plus 128 contexts 174 description: | 175 Interrupt list, with the first #global-interrupts entries corresponding to 176 the global interrupts and any following entries corresponding to context 177 interrupts, specified in order of their indexing by the SMMU. 178 179 For SMMUv2 implementations, there must be exactly one interrupt per 180 context bank. In the case of a single, combined interrupt, it must be 181 listed multiple times. 182 183 dma-coherent: 184 description: | 185 Present if page table walks made by the SMMU are cache coherent with the 186 CPU. 187 188 NOTE: this only applies to the SMMU itself, not masters connected 189 upstream of the SMMU. 190 191 calxeda,smmu-secure-config-access: 192 type: boolean 193 description: 194 Enable proper handling of buggy implementations that always use secure 195 access to SMMU configuration registers. In this case non-secure aliases of 196 secure registers have to be used during SMMU configuration. 197 198 stream-match-mask: 199 $ref: /schemas/types.yaml#/definitions/uint32 200 description: | 201 For SMMUs supporting stream matching and using #iommu-cells = <1>, 202 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 203 be programmed into the SMRn.MASK field of every stream match register 204 used). For cases where it is desirable to ignore some portion of every 205 Stream ID (e.g. for certain MMU-500 configurations given globally unique 206 input IDs). This property is not valid for SMMUs using stream indexing, or 207 using stream matching with #iommu-cells = <2>, and may be ignored if 208 present in such cases. 209 210 clock-names: 211 minItems: 1 212 maxItems: 7 213 214 clocks: 215 minItems: 1 216 maxItems: 7 217 218 power-domains: 219 minItems: 1 220 maxItems: 3 221 222 nvidia,memory-controller: 223 description: | 224 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 225 The memory controller needs to be programmed with a mapping of memory 226 client IDs to ARM SMMU stream IDs. 227 228 If this property is absent, the mapping programmed by early firmware 229 will be used and it is not guaranteed that IOMMU translations will be 230 enabled for any given device. 231 $ref: /schemas/types.yaml#/definitions/phandle 232 233required: 234 - compatible 235 - reg 236 - '#global-interrupts' 237 - '#iommu-cells' 238 - interrupts 239 240additionalProperties: false 241 242allOf: 243 - if: 244 properties: 245 compatible: 246 contains: 247 enum: 248 - nvidia,tegra186-smmu 249 - nvidia,tegra194-smmu 250 - nvidia,tegra234-smmu 251 then: 252 properties: 253 reg: 254 minItems: 1 255 maxItems: 2 256 257 # The reference to the memory controller is required to ensure that the 258 # memory client to stream ID mapping can be done synchronously with the 259 # IOMMU attachment. 260 required: 261 - nvidia,memory-controller 262 else: 263 properties: 264 reg: 265 maxItems: 1 266 267 - if: 268 properties: 269 compatible: 270 contains: 271 enum: 272 - qcom,msm8998-smmu-v2 273 - qcom,sdm630-smmu-v2 274 - qcom,sm6375-smmu-v2 275 then: 276 anyOf: 277 - properties: 278 clock-names: 279 items: 280 - const: bus 281 clocks: 282 items: 283 - description: bus clock required for downstream bus access and for 284 the smmu ptw 285 - properties: 286 clock-names: 287 items: 288 - const: iface 289 - const: mem 290 - const: mem_iface 291 clocks: 292 items: 293 - description: interface clock required to access smmu's registers 294 through the TCU's programming interface. 295 - description: bus clock required for memory access 296 - description: bus clock required for GPU memory access 297 - properties: 298 clock-names: 299 items: 300 - const: iface-mm 301 - const: iface-smmu 302 - const: bus-mm 303 - const: bus-smmu 304 clocks: 305 items: 306 - description: interface clock required to access mnoc's registers 307 through the TCU's programming interface. 308 - description: interface clock required to access smmu's registers 309 through the TCU's programming interface. 310 - description: bus clock required for downstream bus access 311 - description: bus clock required for the smmu ptw 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,msm8996-smmu-v2 319 - qcom,sc7180-smmu-v2 320 - qcom,sdm845-smmu-v2 321 then: 322 properties: 323 clock-names: 324 items: 325 - const: bus 326 - const: iface 327 328 clocks: 329 items: 330 - description: bus clock required for downstream bus access and for 331 the smmu ptw 332 - description: interface clock required to access smmu's registers 333 through the TCU's programming interface. 334 335 - if: 336 properties: 337 compatible: 338 contains: 339 enum: 340 - qcom,sa8775p-smmu-500 341 - qcom,sc7280-smmu-500 342 - qcom,sc8280xp-smmu-500 343 then: 344 properties: 345 clock-names: 346 items: 347 - const: gcc_gpu_memnoc_gfx_clk 348 - const: gcc_gpu_snoc_dvm_gfx_clk 349 - const: gpu_cc_ahb_clk 350 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 351 - const: gpu_cc_cx_gmu_clk 352 - const: gpu_cc_hub_cx_int_clk 353 - const: gpu_cc_hub_aon_clk 354 355 clocks: 356 items: 357 - description: GPU memnoc_gfx clock 358 - description: GPU snoc_dvm_gfx clock 359 - description: GPU ahb clock 360 - description: GPU hlos1_vote_GPU smmu clock 361 - description: GPU cx_gmu clock 362 - description: GPU hub_cx_int clock 363 - description: GPU hub_aon clock 364 365 - if: 366 properties: 367 compatible: 368 contains: 369 enum: 370 - qcom,sm6350-smmu-v2 371 - qcom,sm8150-smmu-500 372 - qcom,sm8250-smmu-500 373 then: 374 properties: 375 clock-names: 376 items: 377 - const: ahb 378 - const: bus 379 - const: iface 380 381 clocks: 382 items: 383 - description: bus clock required for AHB bus access 384 - description: bus clock required for downstream bus access and for 385 the smmu ptw 386 - description: interface clock required to access smmu's registers 387 through the TCU's programming interface. 388 389 - if: 390 properties: 391 compatible: 392 items: 393 - enum: 394 - qcom,sm6115-smmu-500 395 - qcom,sm6125-smmu-500 396 - const: qcom,adreno-smmu 397 - const: qcom,smmu-500 398 - const: arm,mmu-500 399 then: 400 properties: 401 clock-names: 402 items: 403 - const: mem 404 - const: hlos 405 - const: iface 406 407 clocks: 408 items: 409 - description: GPU memory bus clock 410 - description: Voter clock required for HLOS SMMU access 411 - description: Interface clock required for register access 412 413 # Disallow clocks for all other platforms with specific compatibles 414 - if: 415 properties: 416 compatible: 417 contains: 418 enum: 419 - cavium,smmu-v2 420 - marvell,ap806-smmu-500 421 - nvidia,smmu-500 422 - qcom,qcm2290-smmu-500 423 - qcom,qdu1000-smmu-500 424 - qcom,sc7180-smmu-500 425 - qcom,sc8180x-smmu-500 426 - qcom,sdm670-smmu-500 427 - qcom,sdm845-smmu-500 428 - qcom,sdx55-smmu-500 429 - qcom,sdx65-smmu-500 430 - qcom,sm6350-smmu-500 431 - qcom,sm6375-smmu-500 432 - qcom,sm8350-smmu-500 433 - qcom,sm8450-smmu-500 434 - qcom,sm8550-smmu-500 435 then: 436 properties: 437 clock-names: false 438 clocks: false 439 440 - if: 441 properties: 442 compatible: 443 contains: 444 const: qcom,sm6375-smmu-500 445 then: 446 properties: 447 power-domains: 448 items: 449 - description: SNoC MMU TBU RT GDSC 450 - description: SNoC MMU TBU NRT GDSC 451 - description: SNoC TURING MMU TBU0 GDSC 452 453 required: 454 - power-domains 455 else: 456 properties: 457 power-domains: 458 maxItems: 1 459 460examples: 461 - |+ 462 /* SMMU with stream matching or stream indexing */ 463 smmu1: iommu@ba5e0000 { 464 compatible = "arm,smmu-v1"; 465 reg = <0xba5e0000 0x10000>; 466 #global-interrupts = <2>; 467 interrupts = <0 32 4>, 468 <0 33 4>, 469 <0 34 4>, /* This is the first context interrupt */ 470 <0 35 4>, 471 <0 36 4>, 472 <0 37 4>; 473 #iommu-cells = <1>; 474 }; 475 476 /* device with two stream IDs, 0 and 7 */ 477 master1 { 478 iommus = <&smmu1 0>, 479 <&smmu1 7>; 480 }; 481 482 483 /* SMMU with stream matching */ 484 smmu2: iommu@ba5f0000 { 485 compatible = "arm,smmu-v1"; 486 reg = <0xba5f0000 0x10000>; 487 #global-interrupts = <2>; 488 interrupts = <0 38 4>, 489 <0 39 4>, 490 <0 40 4>, /* This is the first context interrupt */ 491 <0 41 4>, 492 <0 42 4>, 493 <0 43 4>; 494 #iommu-cells = <2>; 495 }; 496 497 /* device with stream IDs 0 and 7 */ 498 master2 { 499 iommus = <&smmu2 0 0>, 500 <&smmu2 7 0>; 501 }; 502 503 /* device with stream IDs 1, 17, 33 and 49 */ 504 master3 { 505 iommus = <&smmu2 1 0x30>; 506 }; 507 508 509 /* ARM MMU-500 with 10-bit stream ID input configuration */ 510 smmu3: iommu@ba600000 { 511 compatible = "arm,mmu-500", "arm,smmu-v2"; 512 reg = <0xba600000 0x10000>; 513 #global-interrupts = <2>; 514 interrupts = <0 44 4>, 515 <0 45 4>, 516 <0 46 4>, /* This is the first context interrupt */ 517 <0 47 4>, 518 <0 48 4>, 519 <0 49 4>; 520 #iommu-cells = <1>; 521 /* always ignore appended 5-bit TBU number */ 522 stream-match-mask = <0x7c00>; 523 }; 524 525 bus { 526 /* bus whose child devices emit one unique 10-bit stream 527 ID each, but may master through multiple SMMU TBUs */ 528 iommu-map = <0 &smmu3 0 0x400>; 529 530 531 }; 532 533 - |+ 534 /* Qcom's arm,smmu-v2 implementation */ 535 #include <dt-bindings/interrupt-controller/arm-gic.h> 536 #include <dt-bindings/interrupt-controller/irq.h> 537 smmu4: iommu@d00000 { 538 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 539 reg = <0xd00000 0x10000>; 540 541 #global-interrupts = <1>; 542 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 545 #iommu-cells = <1>; 546 power-domains = <&mmcc 0>; 547 548 clocks = <&mmcc 123>, 549 <&mmcc 124>; 550 clock-names = "bus", "iface"; 551 }; 552