1*4966dfe1SQin Jian# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4966dfe1SQin Jian# Copyright (C) Sunplus Co., Ltd. 2021
3*4966dfe1SQin Jian%YAML 1.2
4*4966dfe1SQin Jian---
5*4966dfe1SQin Jian$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
6*4966dfe1SQin Jian$schema: http://devicetree.org/meta-schemas/core.yaml#
7*4966dfe1SQin Jian
8*4966dfe1SQin Jiantitle: Sunplus SP7021 SoC Interrupt Controller
9*4966dfe1SQin Jian
10*4966dfe1SQin Jianmaintainers:
11*4966dfe1SQin Jian  - Qin Jian <qinjian@cqplus1.com>
12*4966dfe1SQin Jian
13*4966dfe1SQin Jianproperties:
14*4966dfe1SQin Jian  compatible:
15*4966dfe1SQin Jian    items:
16*4966dfe1SQin Jian      - const: sunplus,sp7021-intc
17*4966dfe1SQin Jian
18*4966dfe1SQin Jian  reg:
19*4966dfe1SQin Jian    maxItems: 2
20*4966dfe1SQin Jian    description:
21*4966dfe1SQin Jian      Specifies base physical address(s) and size of the controller regs.
22*4966dfe1SQin Jian      The 1st region include type/polarity/priority/mask regs.
23*4966dfe1SQin Jian      The 2nd region include clear/masked_ext0/masked_ext1/group regs.
24*4966dfe1SQin Jian
25*4966dfe1SQin Jian  interrupt-controller: true
26*4966dfe1SQin Jian
27*4966dfe1SQin Jian  "#interrupt-cells":
28*4966dfe1SQin Jian    const: 2
29*4966dfe1SQin Jian    description:
30*4966dfe1SQin Jian      The first cell is the IRQ number, the second cell is the trigger
31*4966dfe1SQin Jian      type as defined in interrupt.txt in this directory.
32*4966dfe1SQin Jian
33*4966dfe1SQin Jian  interrupts:
34*4966dfe1SQin Jian    maxItems: 2
35*4966dfe1SQin Jian    description:
36*4966dfe1SQin Jian      EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt
37*4966dfe1SQin Jian      controller.
38*4966dfe1SQin Jian
39*4966dfe1SQin Jianrequired:
40*4966dfe1SQin Jian  - compatible
41*4966dfe1SQin Jian  - reg
42*4966dfe1SQin Jian  - interrupt-controller
43*4966dfe1SQin Jian  - "#interrupt-cells"
44*4966dfe1SQin Jian  - interrupts
45*4966dfe1SQin Jian
46*4966dfe1SQin JianadditionalProperties: false
47*4966dfe1SQin Jian
48*4966dfe1SQin Jianexamples:
49*4966dfe1SQin Jian  - |
50*4966dfe1SQin Jian    #include <dt-bindings/interrupt-controller/arm-gic.h>
51*4966dfe1SQin Jian
52*4966dfe1SQin Jian    intc: interrupt-controller@9c000780 {
53*4966dfe1SQin Jian        compatible = "sunplus,sp7021-intc";
54*4966dfe1SQin Jian        reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
55*4966dfe1SQin Jian        interrupt-controller;
56*4966dfe1SQin Jian        #interrupt-cells = <2>;
57*4966dfe1SQin Jian        interrupt-parent = <&gic>;
58*4966dfe1SQin Jian        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
59*4966dfe1SQin Jian                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
60*4966dfe1SQin Jian    };
61*4966dfe1SQin Jian
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