1* ARC-HS Interrupt Distribution Unit
2
3  This optional 2nd level interrupt controller can be used in SMP configurations for
4  dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
5
6Properties:
7
8- compatible: "snps,archs-idu-intc"
9- interrupt-controller: This is an interrupt controller.
10- interrupt-parent: <reference to parent core intc>
11- #interrupt-cells: Must be <1>.
12
13  Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
14  of the particular interrupt line of IDU corresponds to the line N+24 of the
15  core interrupt controller.
16
17  intc accessed via the special ARC AUX register interface, hence "reg" property
18  is not specified.
19
20Example:
21	core_intc: core-interrupt-controller {
22		compatible = "snps,archs-intc";
23		interrupt-controller;
24		#interrupt-cells = <1>;
25	};
26
27	idu_intc: idu-interrupt-controller {
28		compatible = "snps,archs-idu-intc";
29		interrupt-controller;
30		interrupt-parent = <&core_intc>;
31		#interrupt-cells = <1>;
32	};
33
34	some_device: serial@c0fc1000 {
35		interrupt-parent = <&idu_intc>;
36		interrupts = <0>;	/* upstream idu IRQ #24 */
37	};
38