1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  While the PLIC supports both edge-triggered and level-triggered interrupts,
30  interrupt handlers are oblivious to this distinction and therefore it is not
31  specified in the PLIC device-tree binding.
32
33  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
34  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35  contains a specific memory layout, which is documented in chapter 8 of the
36  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
37
38maintainers:
39  - Sagar Kadam <sagar.kadam@sifive.com>
40  - Paul Walmsley  <paul.walmsley@sifive.com>
41  - Palmer Dabbelt <palmer@dabbelt.com>
42
43properties:
44  compatible:
45    items:
46      - enum:
47          - sifive,fu540-c000-plic
48          - starfive,jh7100-plic
49          - canaan,k210-plic
50      - const: sifive,plic-1.0.0
51
52  reg:
53    maxItems: 1
54
55  '#address-cells':
56    const: 0
57
58  '#interrupt-cells':
59    const: 1
60
61  interrupt-controller: true
62
63  interrupts-extended:
64    minItems: 1
65    maxItems: 15872
66    description:
67      Specifies which contexts are connected to the PLIC, with "-1" specifying
68      that a context is not present. Each node pointed to should be a
69      riscv,cpu-intc node, which has a riscv node as parent.
70
71  riscv,ndev:
72    $ref: "/schemas/types.yaml#/definitions/uint32"
73    description:
74      Specifies how many external interrupts are supported by this controller.
75
76required:
77  - compatible
78  - '#address-cells'
79  - '#interrupt-cells'
80  - interrupt-controller
81  - reg
82  - interrupts-extended
83  - riscv,ndev
84
85additionalProperties: false
86
87examples:
88  - |
89    plic: interrupt-controller@c000000 {
90      #address-cells = <0>;
91      #interrupt-cells = <1>;
92      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
93      interrupt-controller;
94      interrupts-extended = <&cpu0_intc 11>,
95                            <&cpu1_intc 11>, <&cpu1_intc 9>,
96                            <&cpu2_intc 11>, <&cpu2_intc 9>,
97                            <&cpu3_intc 11>, <&cpu3_intc 9>,
98                            <&cpu4_intc 11>, <&cpu4_intc 9>;
99      reg = <0xc000000 0x4000000>;
100      riscv,ndev = <10>;
101    };
102