1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  While the PLIC supports both edge-triggered and level-triggered interrupts,
30  interrupt handlers are oblivious to this distinction and therefore it is not
31  specified in the PLIC device-tree binding.
32
33  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
34  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35  contains a specific memory layout, which is documented in chapter 8 of the
36  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
37
38  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
39  T-HEAD PLIC implementation requires setting a delegation bit to allow access
40  from S-mode. So add thead,c900-plic to distinguish them.
41
42maintainers:
43  - Sagar Kadam <sagar.kadam@sifive.com>
44  - Paul Walmsley  <paul.walmsley@sifive.com>
45  - Palmer Dabbelt <palmer@dabbelt.com>
46
47properties:
48  compatible:
49    oneOf:
50      - items:
51          - enum:
52              - sifive,fu540-c000-plic
53              - starfive,jh7100-plic
54              - canaan,k210-plic
55          - const: sifive,plic-1.0.0
56      - items:
57          - enum:
58              - allwinner,sun20i-d1-plic
59          - const: thead,c900-plic
60
61  reg:
62    maxItems: 1
63
64  '#address-cells':
65    const: 0
66
67  '#interrupt-cells':
68    const: 1
69
70  interrupt-controller: true
71
72  interrupts-extended:
73    minItems: 1
74    maxItems: 15872
75    description:
76      Specifies which contexts are connected to the PLIC, with "-1" specifying
77      that a context is not present. Each node pointed to should be a
78      riscv,cpu-intc node, which has a riscv node as parent.
79
80  riscv,ndev:
81    $ref: "/schemas/types.yaml#/definitions/uint32"
82    description:
83      Specifies how many external interrupts are supported by this controller.
84
85required:
86  - compatible
87  - '#address-cells'
88  - '#interrupt-cells'
89  - interrupt-controller
90  - reg
91  - interrupts-extended
92  - riscv,ndev
93
94additionalProperties: false
95
96examples:
97  - |
98    plic: interrupt-controller@c000000 {
99      #address-cells = <0>;
100      #interrupt-cells = <1>;
101      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
102      interrupt-controller;
103      interrupts-extended = <&cpu0_intc 11>,
104                            <&cpu1_intc 11>, <&cpu1_intc 9>,
105                            <&cpu2_intc 11>, <&cpu2_intc 9>,
106                            <&cpu3_intc 11>, <&cpu3_intc 9>,
107                            <&cpu4_intc 11>, <&cpu4_intc 9>;
108      reg = <0xc000000 0x4000000>;
109      riscv,ndev = <10>;
110    };
111