1c825a081SSagar Kadam# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2c825a081SSagar Kadam# Copyright (C) 2020 SiFive, Inc. 3c825a081SSagar Kadam%YAML 1.2 4c825a081SSagar Kadam--- 5c825a081SSagar Kadam$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6c825a081SSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml# 7c825a081SSagar Kadam 8c825a081SSagar Kadamtitle: SiFive Platform-Level Interrupt Controller (PLIC) 9c825a081SSagar Kadam 10c825a081SSagar Kadamdescription: 11c825a081SSagar Kadam SiFive SOCs include an implementation of the Platform-Level Interrupt Controller 12c825a081SSagar Kadam (PLIC) high-level specification in the RISC-V Privileged Architecture 13c825a081SSagar Kadam specification. The PLIC connects all external interrupts in the system to all 14c825a081SSagar Kadam hart contexts in the system, via the external interrupt source in each hart. 15c825a081SSagar Kadam 16c825a081SSagar Kadam A hart context is a privilege mode in a hardware execution thread. For example, 17c825a081SSagar Kadam in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 18c825a081SSagar Kadam privilege modes per hart; machine mode and supervisor mode. 19c825a081SSagar Kadam 20c825a081SSagar Kadam Each interrupt can be enabled on per-context basis. Any context can claim 21c825a081SSagar Kadam a pending enabled interrupt and then release it once it has been handled. 22c825a081SSagar Kadam 23c825a081SSagar Kadam Each interrupt has a configurable priority. Higher priority interrupts are 24c825a081SSagar Kadam serviced first. Each context can specify a priority threshold. Interrupts 25c825a081SSagar Kadam with priority below this threshold will not cause the PLIC to raise its 26c825a081SSagar Kadam interrupt line leading to the context. 27c825a081SSagar Kadam 28c825a081SSagar Kadam While the PLIC supports both edge-triggered and level-triggered interrupts, 29c825a081SSagar Kadam interrupt handlers are oblivious to this distinction and therefore it is not 30c825a081SSagar Kadam specified in the PLIC device-tree binding. 31c825a081SSagar Kadam 32c825a081SSagar Kadam While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 33c825a081SSagar Kadam "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 34c825a081SSagar Kadam contains a specific memory layout, which is documented in chapter 8 of the 35c825a081SSagar Kadam SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 36c825a081SSagar Kadam 37c825a081SSagar Kadammaintainers: 38c825a081SSagar Kadam - Sagar Kadam <sagar.kadam@sifive.com> 39c825a081SSagar Kadam - Paul Walmsley <paul.walmsley@sifive.com> 40c825a081SSagar Kadam - Palmer Dabbelt <palmer@dabbelt.com> 41c825a081SSagar Kadam 42c825a081SSagar Kadamproperties: 43c825a081SSagar Kadam compatible: 44c825a081SSagar Kadam items: 45c825a081SSagar Kadam - const: sifive,fu540-c000-plic 46c825a081SSagar Kadam - const: sifive,plic-1.0.0 47c825a081SSagar Kadam 48c825a081SSagar Kadam reg: 49c825a081SSagar Kadam maxItems: 1 50c825a081SSagar Kadam 51c825a081SSagar Kadam '#address-cells': 52c825a081SSagar Kadam const: 0 53c825a081SSagar Kadam 54c825a081SSagar Kadam '#interrupt-cells': 55c825a081SSagar Kadam const: 1 56c825a081SSagar Kadam 57c825a081SSagar Kadam interrupt-controller: true 58c825a081SSagar Kadam 59c825a081SSagar Kadam interrupts-extended: 60c825a081SSagar Kadam minItems: 1 61c825a081SSagar Kadam description: 62c825a081SSagar Kadam Specifies which contexts are connected to the PLIC, with "-1" specifying 63c825a081SSagar Kadam that a context is not present. Each node pointed to should be a 64c825a081SSagar Kadam riscv,cpu-intc node, which has a riscv node as parent. 65c825a081SSagar Kadam 66c825a081SSagar Kadam riscv,ndev: 67c825a081SSagar Kadam $ref: "/schemas/types.yaml#/definitions/uint32" 68c825a081SSagar Kadam description: 69c825a081SSagar Kadam Specifies how many external interrupts are supported by this controller. 70c825a081SSagar Kadam 71c825a081SSagar Kadamrequired: 72c825a081SSagar Kadam - compatible 73c825a081SSagar Kadam - '#address-cells' 74c825a081SSagar Kadam - '#interrupt-cells' 75c825a081SSagar Kadam - interrupt-controller 76c825a081SSagar Kadam - reg 77c825a081SSagar Kadam - interrupts-extended 78c825a081SSagar Kadam - riscv,ndev 79c825a081SSagar Kadam 80c825a081SSagar KadamadditionalProperties: false 81c825a081SSagar Kadam 82c825a081SSagar Kadamexamples: 83c825a081SSagar Kadam - | 84c825a081SSagar Kadam plic: interrupt-controller@c000000 { 85c825a081SSagar Kadam #address-cells = <0>; 86c825a081SSagar Kadam #interrupt-cells = <1>; 87c825a081SSagar Kadam compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 88c825a081SSagar Kadam interrupt-controller; 89c825a081SSagar Kadam interrupts-extended = < 90c825a081SSagar Kadam &cpu0_intc 11 91c825a081SSagar Kadam &cpu1_intc 11 &cpu1_intc 9 92c825a081SSagar Kadam &cpu2_intc 11 &cpu2_intc 9 93c825a081SSagar Kadam &cpu3_intc 11 &cpu3_intc 9 94c825a081SSagar Kadam &cpu4_intc 11 &cpu4_intc 9>; 95c825a081SSagar Kadam reg = <0xc000000 0x4000000>; 96c825a081SSagar Kadam riscv,ndev = <10>; 97c825a081SSagar Kadam }; 98