1c825a081SSagar Kadam# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2c825a081SSagar Kadam# Copyright (C) 2020 SiFive, Inc. 3c825a081SSagar Kadam%YAML 1.2 4c825a081SSagar Kadam--- 5c825a081SSagar Kadam$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6c825a081SSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml# 7c825a081SSagar Kadam 8c825a081SSagar Kadamtitle: SiFive Platform-Level Interrupt Controller (PLIC) 9c825a081SSagar Kadam 10c825a081SSagar Kadamdescription: 11*90ddcd64SDamien Le Moal SiFive SoCs and other RISC-V SoCs include an implementation of the 12*90ddcd64SDamien Le Moal Platform-Level Interrupt Controller (PLIC) high-level specification in 13*90ddcd64SDamien Le Moal the RISC-V Privileged Architecture specification. The PLIC connects all 14*90ddcd64SDamien Le Moal external interrupts in the system to all hart contexts in the system, via 15*90ddcd64SDamien Le Moal the external interrupt source in each hart. 16c825a081SSagar Kadam 17c825a081SSagar Kadam A hart context is a privilege mode in a hardware execution thread. For example, 18c825a081SSagar Kadam in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 19c825a081SSagar Kadam privilege modes per hart; machine mode and supervisor mode. 20c825a081SSagar Kadam 21c825a081SSagar Kadam Each interrupt can be enabled on per-context basis. Any context can claim 22c825a081SSagar Kadam a pending enabled interrupt and then release it once it has been handled. 23c825a081SSagar Kadam 24c825a081SSagar Kadam Each interrupt has a configurable priority. Higher priority interrupts are 25c825a081SSagar Kadam serviced first. Each context can specify a priority threshold. Interrupts 26c825a081SSagar Kadam with priority below this threshold will not cause the PLIC to raise its 27c825a081SSagar Kadam interrupt line leading to the context. 28c825a081SSagar Kadam 29c825a081SSagar Kadam While the PLIC supports both edge-triggered and level-triggered interrupts, 30c825a081SSagar Kadam interrupt handlers are oblivious to this distinction and therefore it is not 31c825a081SSagar Kadam specified in the PLIC device-tree binding. 32c825a081SSagar Kadam 33c825a081SSagar Kadam While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 34c825a081SSagar Kadam "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 35c825a081SSagar Kadam contains a specific memory layout, which is documented in chapter 8 of the 36c825a081SSagar Kadam SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 37c825a081SSagar Kadam 38c825a081SSagar Kadammaintainers: 39c825a081SSagar Kadam - Sagar Kadam <sagar.kadam@sifive.com> 40c825a081SSagar Kadam - Paul Walmsley <paul.walmsley@sifive.com> 41c825a081SSagar Kadam - Palmer Dabbelt <palmer@dabbelt.com> 42c825a081SSagar Kadam 43c825a081SSagar Kadamproperties: 44c825a081SSagar Kadam compatible: 45c825a081SSagar Kadam items: 46*90ddcd64SDamien Le Moal - enum: 47*90ddcd64SDamien Le Moal - sifive,fu540-c000-plic 48*90ddcd64SDamien Le Moal - canaan,k210-plic 49c825a081SSagar Kadam - const: sifive,plic-1.0.0 50c825a081SSagar Kadam 51c825a081SSagar Kadam reg: 52c825a081SSagar Kadam maxItems: 1 53c825a081SSagar Kadam 54c825a081SSagar Kadam '#address-cells': 55c825a081SSagar Kadam const: 0 56c825a081SSagar Kadam 57c825a081SSagar Kadam '#interrupt-cells': 58c825a081SSagar Kadam const: 1 59c825a081SSagar Kadam 60c825a081SSagar Kadam interrupt-controller: true 61c825a081SSagar Kadam 62c825a081SSagar Kadam interrupts-extended: 63c825a081SSagar Kadam minItems: 1 64c825a081SSagar Kadam description: 65c825a081SSagar Kadam Specifies which contexts are connected to the PLIC, with "-1" specifying 66c825a081SSagar Kadam that a context is not present. Each node pointed to should be a 67c825a081SSagar Kadam riscv,cpu-intc node, which has a riscv node as parent. 68c825a081SSagar Kadam 69c825a081SSagar Kadam riscv,ndev: 70c825a081SSagar Kadam $ref: "/schemas/types.yaml#/definitions/uint32" 71c825a081SSagar Kadam description: 72c825a081SSagar Kadam Specifies how many external interrupts are supported by this controller. 73c825a081SSagar Kadam 74c825a081SSagar Kadamrequired: 75c825a081SSagar Kadam - compatible 76c825a081SSagar Kadam - '#address-cells' 77c825a081SSagar Kadam - '#interrupt-cells' 78c825a081SSagar Kadam - interrupt-controller 79c825a081SSagar Kadam - reg 80c825a081SSagar Kadam - interrupts-extended 81c825a081SSagar Kadam - riscv,ndev 82c825a081SSagar Kadam 83c825a081SSagar KadamadditionalProperties: false 84c825a081SSagar Kadam 85c825a081SSagar Kadamexamples: 86c825a081SSagar Kadam - | 87c825a081SSagar Kadam plic: interrupt-controller@c000000 { 88c825a081SSagar Kadam #address-cells = <0>; 89c825a081SSagar Kadam #interrupt-cells = <1>; 90c825a081SSagar Kadam compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 91c825a081SSagar Kadam interrupt-controller; 92c825a081SSagar Kadam interrupts-extended = < 93c825a081SSagar Kadam &cpu0_intc 11 94c825a081SSagar Kadam &cpu1_intc 11 &cpu1_intc 9 95c825a081SSagar Kadam &cpu2_intc 11 &cpu2_intc 9 96c825a081SSagar Kadam &cpu3_intc 11 &cpu3_intc 9 97c825a081SSagar Kadam &cpu4_intc 11 &cpu4_intc 9>; 98c825a081SSagar Kadam reg = <0xc000000 0x4000000>; 99c825a081SSagar Kadam riscv,ndev = <10>; 100c825a081SSagar Kadam }; 101