1c825a081SSagar Kadam# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2c825a081SSagar Kadam# Copyright (C) 2020 SiFive, Inc. 3c825a081SSagar Kadam%YAML 1.2 4c825a081SSagar Kadam--- 5c825a081SSagar Kadam$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6c825a081SSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml# 7c825a081SSagar Kadam 8c825a081SSagar Kadamtitle: SiFive Platform-Level Interrupt Controller (PLIC) 9c825a081SSagar Kadam 10c825a081SSagar Kadamdescription: 1190ddcd64SDamien Le Moal SiFive SoCs and other RISC-V SoCs include an implementation of the 1290ddcd64SDamien Le Moal Platform-Level Interrupt Controller (PLIC) high-level specification in 1390ddcd64SDamien Le Moal the RISC-V Privileged Architecture specification. The PLIC connects all 1490ddcd64SDamien Le Moal external interrupts in the system to all hart contexts in the system, via 1590ddcd64SDamien Le Moal the external interrupt source in each hart. 16c825a081SSagar Kadam 17c825a081SSagar Kadam A hart context is a privilege mode in a hardware execution thread. For example, 18c825a081SSagar Kadam in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 19c825a081SSagar Kadam privilege modes per hart; machine mode and supervisor mode. 20c825a081SSagar Kadam 21c825a081SSagar Kadam Each interrupt can be enabled on per-context basis. Any context can claim 22c825a081SSagar Kadam a pending enabled interrupt and then release it once it has been handled. 23c825a081SSagar Kadam 24c825a081SSagar Kadam Each interrupt has a configurable priority. Higher priority interrupts are 25c825a081SSagar Kadam serviced first. Each context can specify a priority threshold. Interrupts 26c825a081SSagar Kadam with priority below this threshold will not cause the PLIC to raise its 27c825a081SSagar Kadam interrupt line leading to the context. 28c825a081SSagar Kadam 291267d983SLad Prabhakar The PLIC supports both edge-triggered and level-triggered interrupts. For 301267d983SLad Prabhakar edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges 311267d983SLad Prabhakar seen while an interrupt handler is active; the PLIC may either queue them or 321267d983SLad Prabhakar ignore them. In the first case, handlers are oblivious to the trigger type, so 331267d983SLad Prabhakar it is not included in the interrupt specifier. In the second case, software 341267d983SLad Prabhakar needs to know the trigger type, so it can reorder the interrupt flow to avoid 351267d983SLad Prabhakar missing interrupts. This special handling is needed by at least the Renesas 36d60df7fdSSamuel Holland RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC. 37c825a081SSagar Kadam 38c825a081SSagar Kadam While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 39c825a081SSagar Kadam "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 40c825a081SSagar Kadam contains a specific memory layout, which is documented in chapter 8 of the 41c825a081SSagar Kadam SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 42c825a081SSagar Kadam 43321a8be3SGuo Ren The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the 44321a8be3SGuo Ren T-HEAD PLIC implementation requires setting a delegation bit to allow access 45321a8be3SGuo Ren from S-mode. So add thead,c900-plic to distinguish them. 46321a8be3SGuo Ren 47c825a081SSagar Kadammaintainers: 48c825a081SSagar Kadam - Paul Walmsley <paul.walmsley@sifive.com> 49c825a081SSagar Kadam - Palmer Dabbelt <palmer@dabbelt.com> 50c825a081SSagar Kadam 51c825a081SSagar Kadamproperties: 52c825a081SSagar Kadam compatible: 53321a8be3SGuo Ren oneOf: 54321a8be3SGuo Ren - items: 5590ddcd64SDamien Le Moal - enum: 561267d983SLad Prabhakar - renesas,r9a07g043-plic 571267d983SLad Prabhakar - const: andestech,nceplic100 581267d983SLad Prabhakar - items: 591267d983SLad Prabhakar - enum: 6090ddcd64SDamien Le Moal - sifive,fu540-c000-plic 619ac16169SEmil Renner Berthing - starfive,jh7100-plic 6290ddcd64SDamien Le Moal - canaan,k210-plic 63c825a081SSagar Kadam - const: sifive,plic-1.0.0 64321a8be3SGuo Ren - items: 65321a8be3SGuo Ren - enum: 66321a8be3SGuo Ren - allwinner,sun20i-d1-plic 67321a8be3SGuo Ren - const: thead,c900-plic 686e965c9bSConor Dooley - items: 696e965c9bSConor Dooley - const: sifive,plic-1.0.0 706e965c9bSConor Dooley - const: riscv,plic0 716e965c9bSConor Dooley deprecated: true 726e965c9bSConor Dooley description: For the QEMU virt machine only 73c825a081SSagar Kadam 74c825a081SSagar Kadam reg: 75c825a081SSagar Kadam maxItems: 1 76c825a081SSagar Kadam 77c825a081SSagar Kadam '#address-cells': 78c825a081SSagar Kadam const: 0 79c825a081SSagar Kadam 801267d983SLad Prabhakar '#interrupt-cells': true 81c825a081SSagar Kadam 82c825a081SSagar Kadam interrupt-controller: true 83c825a081SSagar Kadam 84c825a081SSagar Kadam interrupts-extended: 85c825a081SSagar Kadam minItems: 1 868fbc16d2SGeert Uytterhoeven maxItems: 15872 87c825a081SSagar Kadam description: 88c825a081SSagar Kadam Specifies which contexts are connected to the PLIC, with "-1" specifying 89c825a081SSagar Kadam that a context is not present. Each node pointed to should be a 90c825a081SSagar Kadam riscv,cpu-intc node, which has a riscv node as parent. 91c825a081SSagar Kadam 92c825a081SSagar Kadam riscv,ndev: 93*43d78445SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 94c825a081SSagar Kadam description: 95c825a081SSagar Kadam Specifies how many external interrupts are supported by this controller. 96c825a081SSagar Kadam 971267d983SLad Prabhakar clocks: true 981267d983SLad Prabhakar 991267d983SLad Prabhakar power-domains: true 1001267d983SLad Prabhakar 1011267d983SLad Prabhakar resets: true 1021267d983SLad Prabhakar 103c825a081SSagar Kadamrequired: 104c825a081SSagar Kadam - compatible 105c825a081SSagar Kadam - '#address-cells' 106c825a081SSagar Kadam - '#interrupt-cells' 107c825a081SSagar Kadam - interrupt-controller 108c825a081SSagar Kadam - reg 109c825a081SSagar Kadam - interrupts-extended 110c825a081SSagar Kadam - riscv,ndev 111c825a081SSagar Kadam 1121267d983SLad PrabhakarallOf: 1131267d983SLad Prabhakar - if: 1141267d983SLad Prabhakar properties: 1151267d983SLad Prabhakar compatible: 1161267d983SLad Prabhakar contains: 1171267d983SLad Prabhakar enum: 1181267d983SLad Prabhakar - andestech,nceplic100 119d60df7fdSSamuel Holland - thead,c900-plic 1201267d983SLad Prabhakar 1211267d983SLad Prabhakar then: 1221267d983SLad Prabhakar properties: 1231267d983SLad Prabhakar '#interrupt-cells': 1241267d983SLad Prabhakar const: 2 1251267d983SLad Prabhakar 1261267d983SLad Prabhakar else: 1271267d983SLad Prabhakar properties: 1281267d983SLad Prabhakar '#interrupt-cells': 1291267d983SLad Prabhakar const: 1 1301267d983SLad Prabhakar 1311267d983SLad Prabhakar - if: 1321267d983SLad Prabhakar properties: 1331267d983SLad Prabhakar compatible: 1341267d983SLad Prabhakar contains: 1351267d983SLad Prabhakar const: renesas,r9a07g043-plic 1361267d983SLad Prabhakar 1371267d983SLad Prabhakar then: 1381267d983SLad Prabhakar properties: 1391267d983SLad Prabhakar clocks: 1401267d983SLad Prabhakar maxItems: 1 1411267d983SLad Prabhakar 1421267d983SLad Prabhakar power-domains: 1431267d983SLad Prabhakar maxItems: 1 1441267d983SLad Prabhakar 1451267d983SLad Prabhakar resets: 1461267d983SLad Prabhakar maxItems: 1 1471267d983SLad Prabhakar 1481267d983SLad Prabhakar required: 1491267d983SLad Prabhakar - clocks 1501267d983SLad Prabhakar - power-domains 1511267d983SLad Prabhakar - resets 1521267d983SLad Prabhakar 153c825a081SSagar KadamadditionalProperties: false 154c825a081SSagar Kadam 155c825a081SSagar Kadamexamples: 156c825a081SSagar Kadam - | 157c825a081SSagar Kadam plic: interrupt-controller@c000000 { 158c825a081SSagar Kadam #address-cells = <0>; 159c825a081SSagar Kadam #interrupt-cells = <1>; 160c825a081SSagar Kadam compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 161c825a081SSagar Kadam interrupt-controller; 162c89e5eb7SGeert Uytterhoeven interrupts-extended = <&cpu0_intc 11>, 163c89e5eb7SGeert Uytterhoeven <&cpu1_intc 11>, <&cpu1_intc 9>, 164c89e5eb7SGeert Uytterhoeven <&cpu2_intc 11>, <&cpu2_intc 9>, 165c89e5eb7SGeert Uytterhoeven <&cpu3_intc 11>, <&cpu3_intc 9>, 166c89e5eb7SGeert Uytterhoeven <&cpu4_intc 11>, <&cpu4_intc 9>; 167c825a081SSagar Kadam reg = <0xc000000 0x4000000>; 168c825a081SSagar Kadam riscv,ndev = <10>; 169c825a081SSagar Kadam }; 170