1c825a081SSagar Kadam# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2c825a081SSagar Kadam# Copyright (C) 2020 SiFive, Inc. 3c825a081SSagar Kadam%YAML 1.2 4c825a081SSagar Kadam--- 5c825a081SSagar Kadam$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6c825a081SSagar Kadam$schema: http://devicetree.org/meta-schemas/core.yaml# 7c825a081SSagar Kadam 8c825a081SSagar Kadamtitle: SiFive Platform-Level Interrupt Controller (PLIC) 9c825a081SSagar Kadam 10c825a081SSagar Kadamdescription: 1190ddcd64SDamien Le Moal SiFive SoCs and other RISC-V SoCs include an implementation of the 1290ddcd64SDamien Le Moal Platform-Level Interrupt Controller (PLIC) high-level specification in 1390ddcd64SDamien Le Moal the RISC-V Privileged Architecture specification. The PLIC connects all 1490ddcd64SDamien Le Moal external interrupts in the system to all hart contexts in the system, via 1590ddcd64SDamien Le Moal the external interrupt source in each hart. 16c825a081SSagar Kadam 17c825a081SSagar Kadam A hart context is a privilege mode in a hardware execution thread. For example, 18c825a081SSagar Kadam in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 19c825a081SSagar Kadam privilege modes per hart; machine mode and supervisor mode. 20c825a081SSagar Kadam 21c825a081SSagar Kadam Each interrupt can be enabled on per-context basis. Any context can claim 22c825a081SSagar Kadam a pending enabled interrupt and then release it once it has been handled. 23c825a081SSagar Kadam 24c825a081SSagar Kadam Each interrupt has a configurable priority. Higher priority interrupts are 25c825a081SSagar Kadam serviced first. Each context can specify a priority threshold. Interrupts 26c825a081SSagar Kadam with priority below this threshold will not cause the PLIC to raise its 27c825a081SSagar Kadam interrupt line leading to the context. 28c825a081SSagar Kadam 29*1267d983SLad Prabhakar The PLIC supports both edge-triggered and level-triggered interrupts. For 30*1267d983SLad Prabhakar edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges 31*1267d983SLad Prabhakar seen while an interrupt handler is active; the PLIC may either queue them or 32*1267d983SLad Prabhakar ignore them. In the first case, handlers are oblivious to the trigger type, so 33*1267d983SLad Prabhakar it is not included in the interrupt specifier. In the second case, software 34*1267d983SLad Prabhakar needs to know the trigger type, so it can reorder the interrupt flow to avoid 35*1267d983SLad Prabhakar missing interrupts. This special handling is needed by at least the Renesas 36*1267d983SLad Prabhakar RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100). 37c825a081SSagar Kadam 38c825a081SSagar Kadam While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 39c825a081SSagar Kadam "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 40c825a081SSagar Kadam contains a specific memory layout, which is documented in chapter 8 of the 41c825a081SSagar Kadam SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 42c825a081SSagar Kadam 43321a8be3SGuo Ren The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the 44321a8be3SGuo Ren T-HEAD PLIC implementation requires setting a delegation bit to allow access 45321a8be3SGuo Ren from S-mode. So add thead,c900-plic to distinguish them. 46321a8be3SGuo Ren 47c825a081SSagar Kadammaintainers: 48c825a081SSagar Kadam - Sagar Kadam <sagar.kadam@sifive.com> 49c825a081SSagar Kadam - Paul Walmsley <paul.walmsley@sifive.com> 50c825a081SSagar Kadam - Palmer Dabbelt <palmer@dabbelt.com> 51c825a081SSagar Kadam 52c825a081SSagar Kadamproperties: 53c825a081SSagar Kadam compatible: 54321a8be3SGuo Ren oneOf: 55321a8be3SGuo Ren - items: 5690ddcd64SDamien Le Moal - enum: 57*1267d983SLad Prabhakar - renesas,r9a07g043-plic 58*1267d983SLad Prabhakar - const: andestech,nceplic100 59*1267d983SLad Prabhakar - items: 60*1267d983SLad Prabhakar - enum: 6190ddcd64SDamien Le Moal - sifive,fu540-c000-plic 629ac16169SEmil Renner Berthing - starfive,jh7100-plic 6390ddcd64SDamien Le Moal - canaan,k210-plic 64c825a081SSagar Kadam - const: sifive,plic-1.0.0 65321a8be3SGuo Ren - items: 66321a8be3SGuo Ren - enum: 67321a8be3SGuo Ren - allwinner,sun20i-d1-plic 68321a8be3SGuo Ren - const: thead,c900-plic 69c825a081SSagar Kadam 70c825a081SSagar Kadam reg: 71c825a081SSagar Kadam maxItems: 1 72c825a081SSagar Kadam 73c825a081SSagar Kadam '#address-cells': 74c825a081SSagar Kadam const: 0 75c825a081SSagar Kadam 76*1267d983SLad Prabhakar '#interrupt-cells': true 77c825a081SSagar Kadam 78c825a081SSagar Kadam interrupt-controller: true 79c825a081SSagar Kadam 80c825a081SSagar Kadam interrupts-extended: 81c825a081SSagar Kadam minItems: 1 828fbc16d2SGeert Uytterhoeven maxItems: 15872 83c825a081SSagar Kadam description: 84c825a081SSagar Kadam Specifies which contexts are connected to the PLIC, with "-1" specifying 85c825a081SSagar Kadam that a context is not present. Each node pointed to should be a 86c825a081SSagar Kadam riscv,cpu-intc node, which has a riscv node as parent. 87c825a081SSagar Kadam 88c825a081SSagar Kadam riscv,ndev: 89c825a081SSagar Kadam $ref: "/schemas/types.yaml#/definitions/uint32" 90c825a081SSagar Kadam description: 91c825a081SSagar Kadam Specifies how many external interrupts are supported by this controller. 92c825a081SSagar Kadam 93*1267d983SLad Prabhakar clocks: true 94*1267d983SLad Prabhakar 95*1267d983SLad Prabhakar power-domains: true 96*1267d983SLad Prabhakar 97*1267d983SLad Prabhakar resets: true 98*1267d983SLad Prabhakar 99c825a081SSagar Kadamrequired: 100c825a081SSagar Kadam - compatible 101c825a081SSagar Kadam - '#address-cells' 102c825a081SSagar Kadam - '#interrupt-cells' 103c825a081SSagar Kadam - interrupt-controller 104c825a081SSagar Kadam - reg 105c825a081SSagar Kadam - interrupts-extended 106c825a081SSagar Kadam - riscv,ndev 107c825a081SSagar Kadam 108*1267d983SLad PrabhakarallOf: 109*1267d983SLad Prabhakar - if: 110*1267d983SLad Prabhakar properties: 111*1267d983SLad Prabhakar compatible: 112*1267d983SLad Prabhakar contains: 113*1267d983SLad Prabhakar enum: 114*1267d983SLad Prabhakar - andestech,nceplic100 115*1267d983SLad Prabhakar 116*1267d983SLad Prabhakar then: 117*1267d983SLad Prabhakar properties: 118*1267d983SLad Prabhakar '#interrupt-cells': 119*1267d983SLad Prabhakar const: 2 120*1267d983SLad Prabhakar 121*1267d983SLad Prabhakar else: 122*1267d983SLad Prabhakar properties: 123*1267d983SLad Prabhakar '#interrupt-cells': 124*1267d983SLad Prabhakar const: 1 125*1267d983SLad Prabhakar 126*1267d983SLad Prabhakar - if: 127*1267d983SLad Prabhakar properties: 128*1267d983SLad Prabhakar compatible: 129*1267d983SLad Prabhakar contains: 130*1267d983SLad Prabhakar const: renesas,r9a07g043-plic 131*1267d983SLad Prabhakar 132*1267d983SLad Prabhakar then: 133*1267d983SLad Prabhakar properties: 134*1267d983SLad Prabhakar clocks: 135*1267d983SLad Prabhakar maxItems: 1 136*1267d983SLad Prabhakar 137*1267d983SLad Prabhakar power-domains: 138*1267d983SLad Prabhakar maxItems: 1 139*1267d983SLad Prabhakar 140*1267d983SLad Prabhakar resets: 141*1267d983SLad Prabhakar maxItems: 1 142*1267d983SLad Prabhakar 143*1267d983SLad Prabhakar required: 144*1267d983SLad Prabhakar - clocks 145*1267d983SLad Prabhakar - power-domains 146*1267d983SLad Prabhakar - resets 147*1267d983SLad Prabhakar 148c825a081SSagar KadamadditionalProperties: false 149c825a081SSagar Kadam 150c825a081SSagar Kadamexamples: 151c825a081SSagar Kadam - | 152c825a081SSagar Kadam plic: interrupt-controller@c000000 { 153c825a081SSagar Kadam #address-cells = <0>; 154c825a081SSagar Kadam #interrupt-cells = <1>; 155c825a081SSagar Kadam compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 156c825a081SSagar Kadam interrupt-controller; 157c89e5eb7SGeert Uytterhoeven interrupts-extended = <&cpu0_intc 11>, 158c89e5eb7SGeert Uytterhoeven <&cpu1_intc 11>, <&cpu1_intc 9>, 159c89e5eb7SGeert Uytterhoeven <&cpu2_intc 11>, <&cpu2_intc 9>, 160c89e5eb7SGeert Uytterhoeven <&cpu3_intc 11>, <&cpu3_intc 9>, 161c89e5eb7SGeert Uytterhoeven <&cpu4_intc 11>, <&cpu4_intc 9>; 162c825a081SSagar Kadam reg = <0xc000000 0x4000000>; 163c825a081SSagar Kadam riscv,ndev = <10>; 164c825a081SSagar Kadam }; 165