1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11  - Geert Uytterhoeven <geert+renesas@glider.be>
12
13description: |
14  IA55 performs various interrupt controls including synchronization for the external
15  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
16  interrupts output by each IP. And it notifies the interrupt to the GIC
17    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
20      stand-up edge detection interrupts)
21
22properties:
23  compatible:
24    items:
25      - enum:
26          - renesas,r9a07g043u-irqc   # RZ/G2UL
27          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
28          - renesas,r9a07g054-irqc    # RZ/V2L
29      - const: renesas,rzg2l-irqc
30
31  '#interrupt-cells':
32    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
33                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
34                 cell is used to specify the flag.
35    const: 2
36
37  '#address-cells':
38    const: 0
39
40  interrupt-controller: true
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    minItems: 41
47    items:
48      - description: NMI interrupt
49      - description: IRQ0 interrupt
50      - description: IRQ1 interrupt
51      - description: IRQ2 interrupt
52      - description: IRQ3 interrupt
53      - description: IRQ4 interrupt
54      - description: IRQ5 interrupt
55      - description: IRQ6 interrupt
56      - description: IRQ7 interrupt
57      - description: GPIO interrupt, TINT0
58      - description: GPIO interrupt, TINT1
59      - description: GPIO interrupt, TINT2
60      - description: GPIO interrupt, TINT3
61      - description: GPIO interrupt, TINT4
62      - description: GPIO interrupt, TINT5
63      - description: GPIO interrupt, TINT6
64      - description: GPIO interrupt, TINT7
65      - description: GPIO interrupt, TINT8
66      - description: GPIO interrupt, TINT9
67      - description: GPIO interrupt, TINT10
68      - description: GPIO interrupt, TINT11
69      - description: GPIO interrupt, TINT12
70      - description: GPIO interrupt, TINT13
71      - description: GPIO interrupt, TINT14
72      - description: GPIO interrupt, TINT15
73      - description: GPIO interrupt, TINT16
74      - description: GPIO interrupt, TINT17
75      - description: GPIO interrupt, TINT18
76      - description: GPIO interrupt, TINT19
77      - description: GPIO interrupt, TINT20
78      - description: GPIO interrupt, TINT21
79      - description: GPIO interrupt, TINT22
80      - description: GPIO interrupt, TINT23
81      - description: GPIO interrupt, TINT24
82      - description: GPIO interrupt, TINT25
83      - description: GPIO interrupt, TINT26
84      - description: GPIO interrupt, TINT27
85      - description: GPIO interrupt, TINT28
86      - description: GPIO interrupt, TINT29
87      - description: GPIO interrupt, TINT30
88      - description: GPIO interrupt, TINT31
89      - description: Bus error interrupt
90
91  interrupt-names:
92    minItems: 41
93    items:
94      - const: nmi
95      - const: irq0
96      - const: irq1
97      - const: irq2
98      - const: irq3
99      - const: irq4
100      - const: irq5
101      - const: irq6
102      - const: irq7
103      - const: tint0
104      - const: tint1
105      - const: tint2
106      - const: tint3
107      - const: tint4
108      - const: tint5
109      - const: tint6
110      - const: tint7
111      - const: tint8
112      - const: tint9
113      - const: tint10
114      - const: tint11
115      - const: tint12
116      - const: tint13
117      - const: tint14
118      - const: tint15
119      - const: tint16
120      - const: tint17
121      - const: tint18
122      - const: tint19
123      - const: tint20
124      - const: tint21
125      - const: tint22
126      - const: tint23
127      - const: tint24
128      - const: tint25
129      - const: tint26
130      - const: tint27
131      - const: tint28
132      - const: tint29
133      - const: tint30
134      - const: tint31
135      - const: bus-err
136
137  clocks:
138    maxItems: 2
139
140  clock-names:
141    items:
142      - const: clk
143      - const: pclk
144
145  power-domains:
146    maxItems: 1
147
148  resets:
149    maxItems: 1
150
151required:
152  - compatible
153  - '#interrupt-cells'
154  - '#address-cells'
155  - interrupt-controller
156  - reg
157  - interrupts
158  - clocks
159  - clock-names
160  - power-domains
161  - resets
162
163allOf:
164  - $ref: /schemas/interrupt-controller.yaml#
165
166  - if:
167      properties:
168        compatible:
169          contains:
170            const: renesas,r9a07g043u-irqc
171    then:
172      properties:
173        interrupts:
174          minItems: 42
175        interrupt-names:
176          minItems: 42
177      required:
178        - interrupt-names
179
180unevaluatedProperties: false
181
182examples:
183  - |
184    #include <dt-bindings/interrupt-controller/arm-gic.h>
185    #include <dt-bindings/clock/r9a07g044-cpg.h>
186
187    irqc: interrupt-controller@110a0000 {
188        compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
189        reg = <0x110a0000 0x10000>;
190        #interrupt-cells = <2>;
191        #address-cells = <0>;
192        interrupt-controller;
193        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
194                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
195                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
196                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
197                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
198                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
199                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
200                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
201                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
202                     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
203                     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
204                     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
205                     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
206                     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
207                     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
208                     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
209                     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
210                     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
211                     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
212                     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
213                     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
214                     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
215                     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
216                     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
217                     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
218                     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
219                     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
220                     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
221                     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
222                     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
223                     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
224                     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
225                     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
226                     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
227                     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
228                     <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
229                     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
230                     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
231                     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
232                     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
233                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
234        interrupt-names = "nmi",
235                          "irq0", "irq1", "irq2", "irq3",
236                          "irq4", "irq5", "irq6", "irq7",
237                          "tint0", "tint1", "tint2", "tint3",
238                          "tint4", "tint5", "tint6", "tint7",
239                          "tint8", "tint9", "tint10", "tint11",
240                          "tint12", "tint13", "tint14", "tint15",
241                          "tint16", "tint17", "tint18", "tint19",
242                          "tint20", "tint21", "tint22", "tint23",
243                          "tint24", "tint25", "tint26", "tint27",
244                          "tint28", "tint29", "tint30", "tint31";
245        clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
246                 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
247        clock-names = "clk", "pclk";
248        power-domains = <&cpg>;
249        resets = <&cpg R9A07G044_IA55_RESETN>;
250    };
251