1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - renesas,irqc-r8a73a4 # R-Mobile APE6 17 - renesas,irqc-r8a7742 # RZ/G1H 18 - renesas,irqc-r8a7743 # RZ/G1M 19 - renesas,irqc-r8a7744 # RZ/G1N 20 - renesas,irqc-r8a7745 # RZ/G1E 21 - renesas,irqc-r8a77470 # RZ/G1C 22 - renesas,irqc-r8a7790 # R-Car H2 23 - renesas,irqc-r8a7791 # R-Car M2-W 24 - renesas,irqc-r8a7792 # R-Car V2H 25 - renesas,irqc-r8a7793 # R-Car M2-N 26 - renesas,irqc-r8a7794 # R-Car E2 27 - renesas,intc-ex-r8a774a1 # RZ/G2M 28 - renesas,intc-ex-r8a774b1 # RZ/G2N 29 - renesas,intc-ex-r8a774c0 # RZ/G2E 30 - renesas,intc-ex-r8a7795 # R-Car H3 31 - renesas,intc-ex-r8a7796 # R-Car M3-W 32 - renesas,intc-ex-r8a77965 # R-Car M3-N 33 - renesas,intc-ex-r8a77970 # R-Car V3M 34 - renesas,intc-ex-r8a77980 # R-Car V3H 35 - renesas,intc-ex-r8a77990 # R-Car E3 36 - renesas,intc-ex-r8a77995 # R-Car D3 37 - const: renesas,irqc 38 39 '#interrupt-cells': 40 # an interrupt index and flags, as defined in interrupts.txt in 41 # this directory 42 const: 2 43 44 interrupt-controller: true 45 46 reg: 47 maxItems: 1 48 49 interrupts: 50 minItems: 1 51 maxItems: 32 52 53 clocks: 54 maxItems: 1 55 56 power-domains: 57 maxItems: 1 58 59 resets: 60 maxItems: 1 61 62required: 63 - compatible 64 - '#interrupt-cells' 65 - interrupt-controller 66 - reg 67 - interrupts 68 - clocks 69 70additionalProperties: false 71 72examples: 73 - | 74 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 75 #include <dt-bindings/interrupt-controller/arm-gic.h> 76 #include <dt-bindings/interrupt-controller/irq.h> 77 78 irqc0: interrupt-controller@e61c0000 { 79 compatible = "renesas,irqc-r8a7790", "renesas,irqc"; 80 #interrupt-cells = <2>; 81 interrupt-controller; 82 reg = <0xe61c0000 0x200>; 83 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 87 clocks = <&cpg CPG_MOD 407>; 88 }; 89