1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Realtek RTL SoC interrupt controller devicetree bindings
8
9description:
10  Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
11  interrupt to be routed to one parent CPU (hardware) interrupt, or left
12  disconnected.
13  All connected input lines from SoC peripherals can be masked individually,
14  and an interrupt status register is present to indicate which interrupts are
15  pending.
16
17maintainers:
18  - Birger Koblitz <mail@birger-koblitz.de>
19  - Bert Vermeulen <bert@biot.com>
20  - John Crispin <john@phrozen.org>
21
22properties:
23  compatible:
24    oneOf:
25      - items:
26          - enum:
27              - realtek,rtl8380-intc
28          - const: realtek,rtl-intc
29      - const: realtek,rtl-intc
30        deprecated: true
31
32  "#interrupt-cells":
33    description:
34      SoC interrupt line index.
35    const: 1
36
37  reg:
38    maxItems: 1
39
40  interrupts:
41    minItems: 1
42    maxItems: 15
43    description:
44      List of parent interrupts, in the order that they are connected to this
45      interrupt router's outputs, starting at the first output.
46
47  interrupt-controller: true
48
49  interrupt-map:
50    deprecated: true
51    description: Describes mapping from SoC interrupts to CPU interrupts
52
53required:
54  - compatible
55  - reg
56  - "#interrupt-cells"
57  - interrupt-controller
58
59allOf:
60  - if:
61      properties:
62        compatible:
63          const: realtek,rtl-intc
64    then:
65      properties:
66        "#address-cells":
67          const: 0
68      required:
69        - "#address-cells"
70        - interrupt-map
71    else:
72      required:
73        - interrupts
74
75additionalProperties: false
76
77examples:
78  - |
79    interrupt-controller@3000 {
80      compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
81      #interrupt-cells = <1>;
82      interrupt-controller;
83      reg = <0x3000 0x18>;
84
85      interrupt-parent = <&cpuintc>;
86      interrupts = <2>, <3>, <4>, <5>, <6>;
87    };
88