1Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 2 3The MISC interrupt controller is a secondary controller for lower priority 4interrupt. 5 6Required Properties: 7- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" 8 as fallback 9- reg: Base address and size of the controllers memory area 10- interrupt-parent: phandle of the parent interrupt controller. 11- interrupts: Interrupt specifier for the controllers interrupt. 12- interrupt-controller : Identifies the node as an interrupt controller 13- #interrupt-cells : Specifies the number of cells needed to encode interrupt 14 source, should be 1 15 16Please refer to interrupts.txt in this directory for details of the common 17Interrupt Controllers bindings used by client devices. 18 19Example: 20 21 interrupt-controller@18060010 { 22 compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc"; 23 reg = <0x18060010 0x4>; 24 25 interrupt-parent = <&cpuintc>; 26 interrupts = <6>; 27 28 interrupt-controller; 29 #interrupt-cells = <1>; 30 }; 31