1c27f29bbSThomas Petazzoni 2c27f29bbSThomas Petazzoni* Marvell ODMI for MSI support 3c27f29bbSThomas Petazzoni 4c27f29bbSThomas PetazzoniSome Marvell SoCs have an On-Die Message Interrupt (ODMI) controller 5c27f29bbSThomas Petazzoniwhich can be used by on-board peripheral for MSI interrupts. 6c27f29bbSThomas Petazzoni 7c27f29bbSThomas PetazzoniRequired properties: 8c27f29bbSThomas Petazzoni 9b009b096SThomas Petazzoni- compatible : The value here should contain: 10b009b096SThomas Petazzoni 11b009b096SThomas Petazzoni "marvell,ap806-odmi-controller", "marvell,odmi-controller". 12c27f29bbSThomas Petazzoni 13c27f29bbSThomas Petazzoni- interrupt,controller : Identifies the node as an interrupt controller. 14c27f29bbSThomas Petazzoni 15c27f29bbSThomas Petazzoni- msi-controller : Identifies the node as an MSI controller. 16c27f29bbSThomas Petazzoni 17c27f29bbSThomas Petazzoni- marvell,odmi-frames : Number of ODMI frames available. Each frame 18c27f29bbSThomas Petazzoni provides a number of events. 19c27f29bbSThomas Petazzoni 20c27f29bbSThomas Petazzoni- reg : List of register definitions, one for each 21c27f29bbSThomas Petazzoni ODMI frame. 22c27f29bbSThomas Petazzoni 23c27f29bbSThomas Petazzoni- marvell,spi-base : List of GIC base SPI interrupts, one for each 24c27f29bbSThomas Petazzoni ODMI frame. Those SPI interrupts are 0-based, 25c27f29bbSThomas Petazzoni i.e marvell,spi-base = <128> will use SPI #96. 26dfab9954SMauro Carvalho Chehab See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 27c27f29bbSThomas Petazzoni for details about the GIC Device Tree binding. 28c27f29bbSThomas Petazzoni 29c27f29bbSThomas PetazzoniExample: 30c27f29bbSThomas Petazzoni 31c27f29bbSThomas Petazzoni odmi: odmi@300000 { 3223299b8cSBaruch Siach compatible = "marvell,ap806-odmi-controller", 33b009b096SThomas Petazzoni "marvell,odmi-controller"; 34c27f29bbSThomas Petazzoni interrupt-controller; 35c27f29bbSThomas Petazzoni msi-controller; 36c27f29bbSThomas Petazzoni marvell,odmi-frames = <4>; 37c27f29bbSThomas Petazzoni reg = <0x300000 0x4000>, 38c27f29bbSThomas Petazzoni <0x304000 0x4000>, 39c27f29bbSThomas Petazzoni <0x308000 0x4000>, 40c27f29bbSThomas Petazzoni <0x30C000 0x4000>; 41c27f29bbSThomas Petazzoni marvell,spi-base = <128>, <136>, <144>, <152>; 42c27f29bbSThomas Petazzoni }; 43