1c27f29bbSThomas Petazzoni 2c27f29bbSThomas Petazzoni* Marvell ODMI for MSI support 3c27f29bbSThomas Petazzoni 4c27f29bbSThomas PetazzoniSome Marvell SoCs have an On-Die Message Interrupt (ODMI) controller 5c27f29bbSThomas Petazzoniwhich can be used by on-board peripheral for MSI interrupts. 6c27f29bbSThomas Petazzoni 7c27f29bbSThomas PetazzoniRequired properties: 8c27f29bbSThomas Petazzoni 9c27f29bbSThomas Petazzoni- compatible : The value here should contain "marvell,odmi-controller". 10c27f29bbSThomas Petazzoni 11c27f29bbSThomas Petazzoni- interrupt,controller : Identifies the node as an interrupt controller. 12c27f29bbSThomas Petazzoni 13c27f29bbSThomas Petazzoni- msi-controller : Identifies the node as an MSI controller. 14c27f29bbSThomas Petazzoni 15c27f29bbSThomas Petazzoni- marvell,odmi-frames : Number of ODMI frames available. Each frame 16c27f29bbSThomas Petazzoni provides a number of events. 17c27f29bbSThomas Petazzoni 18c27f29bbSThomas Petazzoni- reg : List of register definitions, one for each 19c27f29bbSThomas Petazzoni ODMI frame. 20c27f29bbSThomas Petazzoni 21c27f29bbSThomas Petazzoni- marvell,spi-base : List of GIC base SPI interrupts, one for each 22c27f29bbSThomas Petazzoni ODMI frame. Those SPI interrupts are 0-based, 23c27f29bbSThomas Petazzoni i.e marvell,spi-base = <128> will use SPI #96. 24c27f29bbSThomas Petazzoni See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt 25c27f29bbSThomas Petazzoni for details about the GIC Device Tree binding. 26c27f29bbSThomas Petazzoni 27c27f29bbSThomas Petazzoni- interrupt-parent : Reference to the parent interrupt controller. 28c27f29bbSThomas Petazzoni 29c27f29bbSThomas PetazzoniExample: 30c27f29bbSThomas Petazzoni 31c27f29bbSThomas Petazzoni odmi: odmi@300000 { 32c27f29bbSThomas Petazzoni compatible = "marvell,odmi-controller"; 33c27f29bbSThomas Petazzoni interrupt-controller; 34c27f29bbSThomas Petazzoni msi-controller; 35c27f29bbSThomas Petazzoni marvell,odmi-frames = <4>; 36c27f29bbSThomas Petazzoni reg = <0x300000 0x4000>, 37c27f29bbSThomas Petazzoni <0x304000 0x4000>, 38c27f29bbSThomas Petazzoni <0x308000 0x4000>, 39c27f29bbSThomas Petazzoni <0x30C000 0x4000>; 40c27f29bbSThomas Petazzoni marvell,spi-base = <128>, <136>, <144>, <152>; 41c27f29bbSThomas Petazzoni }; 42