1*0305c98cSKeguang Zhang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*0305c98cSKeguang Zhang%YAML 1.2 3*0305c98cSKeguang Zhang--- 4*0305c98cSKeguang Zhang$id: http://devicetree.org/schemas/interrupt-controller/loongson,ls1x-intc.yaml# 5*0305c98cSKeguang Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0305c98cSKeguang Zhang 7*0305c98cSKeguang Zhangtitle: Loongson-1 Interrupt Controller 8*0305c98cSKeguang Zhang 9*0305c98cSKeguang Zhangmaintainers: 10*0305c98cSKeguang Zhang - Keguang Zhang <keguang.zhang@gmail.com> 11*0305c98cSKeguang Zhang 12*0305c98cSKeguang Zhangdescription: 13*0305c98cSKeguang Zhang Loongson-1 interrupt controller is connected to the MIPS core interrupt 14*0305c98cSKeguang Zhang controller, which controls several groups of interrupts. 15*0305c98cSKeguang Zhang 16*0305c98cSKeguang Zhangproperties: 17*0305c98cSKeguang Zhang compatible: 18*0305c98cSKeguang Zhang const: loongson,ls1x-intc 19*0305c98cSKeguang Zhang 20*0305c98cSKeguang Zhang reg: 21*0305c98cSKeguang Zhang maxItems: 1 22*0305c98cSKeguang Zhang 23*0305c98cSKeguang Zhang interrupt-controller: true 24*0305c98cSKeguang Zhang 25*0305c98cSKeguang Zhang '#interrupt-cells': 26*0305c98cSKeguang Zhang const: 2 27*0305c98cSKeguang Zhang 28*0305c98cSKeguang Zhang interrupts: 29*0305c98cSKeguang Zhang maxItems: 1 30*0305c98cSKeguang Zhang 31*0305c98cSKeguang Zhangrequired: 32*0305c98cSKeguang Zhang - compatible 33*0305c98cSKeguang Zhang - reg 34*0305c98cSKeguang Zhang - interrupt-controller 35*0305c98cSKeguang Zhang - '#interrupt-cells' 36*0305c98cSKeguang Zhang - interrupts 37*0305c98cSKeguang Zhang 38*0305c98cSKeguang ZhangadditionalProperties: false 39*0305c98cSKeguang Zhang 40*0305c98cSKeguang Zhangexamples: 41*0305c98cSKeguang Zhang - | 42*0305c98cSKeguang Zhang intc0: interrupt-controller@1fd01040 { 43*0305c98cSKeguang Zhang compatible = "loongson,ls1x-intc"; 44*0305c98cSKeguang Zhang reg = <0x1fd01040 0x18>; 45*0305c98cSKeguang Zhang 46*0305c98cSKeguang Zhang interrupt-controller; 47*0305c98cSKeguang Zhang #interrupt-cells = <2>; 48*0305c98cSKeguang Zhang 49*0305c98cSKeguang Zhang interrupt-parent = <&cpu_intc>; 50*0305c98cSKeguang Zhang interrupts = <2>; 51*0305c98cSKeguang Zhang }; 52