1BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
2
3The BCM2835 contains a custom top-level interrupt controller, which supports
472 interrupt sources using a 2-level register scheme. The interrupt
5controller, or the HW block containing it, is referred to occasionally
6as "armctrl" in the SoC documentation, hence naming of this binding.
7
8The BCM2836 contains the same interrupt controller with the same
9interrupts, but the per-CPU interrupt controller is the root, and an
10interrupt there indicates that the ARMCTRL has an interrupt to handle.
11
12Required properties:
13
14- compatible : should be "brcm,bcm2835-armctrl-ic" or
15                 "brcm,bcm2836-armctrl-ic"
16- reg : Specifies base physical address and size of the registers.
17- interrupt-controller : Identifies the node as an interrupt controller
18- #interrupt-cells : Specifies the number of cells needed to encode an
19  interrupt source. The value shall be 2.
20
21  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
22  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
23  1/2" register.
24
25  The 2nd cell contains the interrupt number within the bank. Valid values
26  are 0..7 for bank 0, and 0..31 for bank 1.
27
28Additional required properties for brcm,bcm2836-armctrl-ic:
29- interrupt-parent : Specifies the parent interrupt controller when this
30  controller is the second level.
31- interrupts : Specifies the interrupt on the parent for this interrupt
32  controller to handle.
33
34The interrupt sources are as follows:
35
36Bank 0:
370: ARM_TIMER
381: ARM_MAILBOX
392: ARM_DOORBELL_0
403: ARM_DOORBELL_1
414: VPU0_HALTED
425: VPU1_HALTED
436: ILLEGAL_TYPE0
447: ILLEGAL_TYPE1
45
46Bank 1:
470: TIMER0
481: TIMER1
492: TIMER2
503: TIMER3
514: CODEC0
525: CODEC1
536: CODEC2
547: VC_JPEG
558: ISP
569: VC_USB
5710: VC_3D
5811: TRANSPOSER
5912: MULTICORESYNC0
6013: MULTICORESYNC1
6114: MULTICORESYNC2
6215: MULTICORESYNC3
6316: DMA0
6417: DMA1
6518: VC_DMA2
6619: VC_DMA3
6720: DMA4
6821: DMA5
6922: DMA6
7023: DMA7
7124: DMA8
7225: DMA9
7326: DMA10
7427: DMA11-14 - shared interrupt for DMA 11 to 14
7528: DMAALL - triggers on all dma interrupts (including chanel 15)
7629: AUX
7730: ARM
7831: VPUDMA
79
80Bank 2:
810: HOSTPORT
821: VIDEOSCALER
832: CCP2TX
843: SDC
854: DSI0
865: AVE
876: CAM0
887: CAM1
898: HDMI0
909: HDMI1
9110: PIXELVALVE1
9211: I2CSPISLV
9312: DSI1
9413: PWA0
9514: PWA1
9615: CPR
9716: SMI
9817: GPIO0
9918: GPIO1
10019: GPIO2
10120: GPIO3
10221: VC_I2C
10322: VC_SPI
10423: VC_I2SPCM
10524: VC_SDIO
10625: VC_UART
10726: SLIMBUS
10827: VEC
10928: CPG
11029: RNG
11130: VC_ARASANSDIO
11231: AVSPMON
113
114Example:
115
116/* BCM2835, first level */
117intc: interrupt-controller {
118	compatible = "brcm,bcm2835-armctrl-ic";
119	reg = <0x7e00b200 0x200>;
120	interrupt-controller;
121	#interrupt-cells = <2>;
122};
123
124/* BCM2836, second level */
125intc: interrupt-controller {
126	compatible = "brcm,bcm2836-armctrl-ic";
127	reg = <0x7e00b200 0x200>;
128	interrupt-controller;
129	#interrupt-cells = <2>;
130
131	interrupt-parent = <&local_intc>;
132	interrupts = <8>;
133};
134