1*4102cf16SFlorian Fainelli# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4102cf16SFlorian Fainelli%YAML 1.2 3*4102cf16SFlorian Fainelli--- 4*4102cf16SFlorian Fainelli$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml# 5*4102cf16SFlorian Fainelli$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4102cf16SFlorian Fainelli 7*4102cf16SFlorian Fainellititle: Broadcom BCM7038-style Level 1 interrupt controller 8*4102cf16SFlorian Fainelli 9*4102cf16SFlorian Fainellidescription: > 10*4102cf16SFlorian Fainelli This block is a first level interrupt controller that is typically connected 11*4102cf16SFlorian Fainelli directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip 12*4102cf16SFlorian Fainelli since BCM7038 has contained this hardware. 13*4102cf16SFlorian Fainelli 14*4102cf16SFlorian Fainelli Key elements of the hardware design include: 15*4102cf16SFlorian Fainelli 16*4102cf16SFlorian Fainelli - 64, 96, 128, or 160 incoming level IRQ lines 17*4102cf16SFlorian Fainelli 18*4102cf16SFlorian Fainelli - Most onchip peripherals are wired directly to an L1 input 19*4102cf16SFlorian Fainelli 20*4102cf16SFlorian Fainelli - A separate instance of the register set for each CPU, allowing individual 21*4102cf16SFlorian Fainelli peripheral IRQs to be routed to any CPU 22*4102cf16SFlorian Fainelli 23*4102cf16SFlorian Fainelli - Atomic mask/unmask operations 24*4102cf16SFlorian Fainelli 25*4102cf16SFlorian Fainelli - No polarity/level/edge settings 26*4102cf16SFlorian Fainelli 27*4102cf16SFlorian Fainelli - No FIFO or priority encoder logic; software is expected to read all 28*4102cf16SFlorian Fainelli 2-5 status words to determine which IRQs are pending 29*4102cf16SFlorian Fainelli 30*4102cf16SFlorian Fainelli If multiple reg ranges and interrupt-parent entries are present on an SMP 31*4102cf16SFlorian Fainelli system, the driver will allow IRQ SMP affinity to be set up through the 32*4102cf16SFlorian Fainelli /proc/irq/ interface. In the simplest possible configuration, only one 33*4102cf16SFlorian Fainelli reg range and one interrupt-parent is needed. 34*4102cf16SFlorian Fainelli 35*4102cf16SFlorian Fainellimaintainers: 36*4102cf16SFlorian Fainelli - Florian Fainelli <f.fainelli@gmail.com> 37*4102cf16SFlorian Fainelli 38*4102cf16SFlorian FainelliallOf: 39*4102cf16SFlorian Fainelli - $ref: /schemas/interrupt-controller.yaml# 40*4102cf16SFlorian Fainelli 41*4102cf16SFlorian Fainelliproperties: 42*4102cf16SFlorian Fainelli compatible: 43*4102cf16SFlorian Fainelli const: brcm,bcm7038-l1-intc 44*4102cf16SFlorian Fainelli 45*4102cf16SFlorian Fainelli reg: 46*4102cf16SFlorian Fainelli description: > 47*4102cf16SFlorian Fainelli Specifies the base physical address and size of the registers 48*4102cf16SFlorian Fainelli the number of supported IRQs is inferred from the size argument 49*4102cf16SFlorian Fainelli 50*4102cf16SFlorian Fainelli interrupt-controller: true 51*4102cf16SFlorian Fainelli 52*4102cf16SFlorian Fainelli "#interrupt-cells": 53*4102cf16SFlorian Fainelli const: 1 54*4102cf16SFlorian Fainelli 55*4102cf16SFlorian Fainelli interrupts: 56*4102cf16SFlorian Fainelli description: > 57*4102cf16SFlorian Fainelli Specifies the interrupt line(s) in the interrupt-parent controller node; 58*4102cf16SFlorian Fainelli valid values depend on the type of parent interrupt controller 59*4102cf16SFlorian Fainelli 60*4102cf16SFlorian Fainelli brcm,irq-can-wake: 61*4102cf16SFlorian Fainelli type: boolean 62*4102cf16SFlorian Fainelli description: > 63*4102cf16SFlorian Fainelli If present, this means the L1 controller can be used as a 64*4102cf16SFlorian Fainelli wakeup source for system suspend/resume. 65*4102cf16SFlorian Fainelli 66*4102cf16SFlorian Fainelli brcm,int-fwd-mask: 67*4102cf16SFlorian Fainelli $ref: /schemas/types.yaml#/definitions/uint32-array 68*4102cf16SFlorian Fainelli description: 69*4102cf16SFlorian Fainelli If present, a bit mask to indicate which interrupts have already been 70*4102cf16SFlorian Fainelli configured by the firmware and should be left unmanaged. This should 71*4102cf16SFlorian Fainelli have one 32-bit word per status/set/clear/mask group. 72*4102cf16SFlorian Fainelli 73*4102cf16SFlorian Fainellirequired: 74*4102cf16SFlorian Fainelli - compatible 75*4102cf16SFlorian Fainelli - reg 76*4102cf16SFlorian Fainelli - interrupt-controller 77*4102cf16SFlorian Fainelli - "#interrupt-cells" 78*4102cf16SFlorian Fainelli - interrupts 79*4102cf16SFlorian Fainelli 80*4102cf16SFlorian FainelliadditionalProperties: false 81*4102cf16SFlorian Fainelli 82*4102cf16SFlorian Fainelliexamples: 83*4102cf16SFlorian Fainelli - | 84*4102cf16SFlorian Fainelli periph_intc: interrupt-controller@1041a400 { 85*4102cf16SFlorian Fainelli compatible = "brcm,bcm7038-l1-intc"; 86*4102cf16SFlorian Fainelli reg = <0x1041a400 0x30>, <0x1041a600 0x30>; 87*4102cf16SFlorian Fainelli interrupt-controller; 88*4102cf16SFlorian Fainelli #interrupt-cells = <1>; 89*4102cf16SFlorian Fainelli interrupt-parent = <&cpu_intc>; 90*4102cf16SFlorian Fainelli interrupts = <2>, <3>; 91*4102cf16SFlorian Fainelli }; 92