1815e7a31SEric AnholtBCM2836 per-CPU interrupt controller 2815e7a31SEric Anholt 3815e7a31SEric AnholtThe BCM2836 has a per-cpu interrupt controller for the timer, PMU 4815e7a31SEric Anholtevents, and SMP IPIs. One of the CPUs may receive interrupts for the 5815e7a31SEric Anholtperipheral (GPU) events, which chain to the BCM2835-style interrupt 6815e7a31SEric Anholtcontroller. 7815e7a31SEric Anholt 8815e7a31SEric AnholtRequired properties: 9815e7a31SEric Anholt 10815e7a31SEric Anholt- compatible: Should be "brcm,bcm2836-l1-intc" 11815e7a31SEric Anholt- reg: Specifies base physical address and size of the 12815e7a31SEric Anholt registers 13815e7a31SEric Anholt- interrupt-controller: Identifies the node as an interrupt controller 14815e7a31SEric Anholt- #interrupt-cells: Specifies the number of cells needed to encode an 1536464580SStefan Wahren interrupt source. The value shall be 2 16815e7a31SEric Anholt 17815e7a31SEric AnholtPlease refer to interrupts.txt in this directory for details of the common 18815e7a31SEric AnholtInterrupt Controllers bindings used by client devices. 19815e7a31SEric Anholt 20815e7a31SEric AnholtThe interrupt sources are as follows: 21815e7a31SEric Anholt 22815e7a31SEric Anholt0: CNTPSIRQ 23815e7a31SEric Anholt1: CNTPNSIRQ 24815e7a31SEric Anholt2: CNTHPIRQ 25815e7a31SEric Anholt3: CNTVIRQ 26815e7a31SEric Anholt8: GPU_FAST 27815e7a31SEric Anholt9: PMU_FAST 28815e7a31SEric Anholt 29815e7a31SEric AnholtExample: 30815e7a31SEric Anholt 31815e7a31SEric Anholtlocal_intc: local_intc { 32815e7a31SEric Anholt compatible = "brcm,bcm2836-l1-intc"; 33815e7a31SEric Anholt reg = <0x40000000 0x100>; 34815e7a31SEric Anholt interrupt-controller; 3536464580SStefan Wahren #interrupt-cells = <2>; 36815e7a31SEric Anholt interrupt-parent = <&local_intc>; 37815e7a31SEric Anholt}; 38