1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Generic Interrupt Controller v1 and v2
8
9maintainers:
10  - Marc Zyngier <marc.zyngier@arm.com>
11
12description: |+
13  ARM SMP cores are often associated with a GIC, providing per processor
14  interrupts (PPI), shared processor interrupts (SPI) and software
15  generated interrupts (SGI).
16
17  Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
18  Secondary GICs are cascaded into the upward interrupt controller and do not
19  have PPIs or SGIs.
20
21allOf:
22  - $ref: /schemas/interrupt-controller.yaml#
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - arm,arm11mp-gic
30              - arm,cortex-a15-gic
31              - arm,cortex-a7-gic
32              - arm,cortex-a5-gic
33              - arm,cortex-a9-gic
34              - arm,eb11mp-gic
35              - arm,gic-400
36              - arm,pl390
37              - arm,tc11mp-gic
38              - nvidia,tegra210-agic
39              - qcom,msm-8660-qgic
40              - qcom,msm-qgic2
41
42      - items:
43          - const: arm,arm1176jzf-devchip-gic
44          - const: arm,arm11mp-gic
45
46      - items:
47          - const: brcm,brahma-b15-gic
48          - const: arm,cortex-a15-gic
49
50  interrupt-controller: true
51
52  "#address-cells":
53    enum: [ 0, 1 ]
54  "#size-cells":
55    const: 1
56
57  "#interrupt-cells":
58    const: 3
59    description: |
60      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
61      interrupts.
62
63      The 2nd cell contains the interrupt number for the interrupt type.
64      SPI interrupts are in the range [0-987].  PPI interrupts are in the
65      range [0-15].
66
67      The 3rd cell is the flags, encoded as follows:
68        bits[3:0] trigger type and level flags.
69          1 = low-to-high edge triggered
70          2 = high-to-low edge triggered (invalid for SPIs)
71          4 = active high level-sensitive
72          8 = active low level-sensitive (invalid for SPIs).
73        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
74        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
75        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
76        Also note that the configurability of PPI interrupts is IMPLEMENTATION
77        DEFINED and as such not guaranteed to be present (most SoC available
78        in 2014 seem to ignore the setting of this flag and use the hardware
79        default value).
80
81  reg:
82    description: |
83      Specifies base physical address(s) and size of the GIC registers. The
84      first region is the GIC distributor register base and size. The 2nd region
85      is the GIC cpu interface register base and size.
86
87      For GICv2 with virtualization extensions, additional regions are
88      required for specifying the base physical address and size of the VGIC
89      registers. The first additional region is the GIC virtual interface
90      control register base and size. The 2nd additional region is the GIC
91      virtual cpu interface register base and size.
92    minItems: 2
93    maxItems: 4
94
95  ranges: true
96
97  interrupts:
98    description: Interrupt source of the parent interrupt controller on
99      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
100      below).
101    maxItems: 1
102
103  cpu-offset:
104    description: per-cpu offset within the distributor and cpu interface
105      regions, used when the GIC doesn't have banked registers. The offset
106      is cpu-offset * cpu-nr.
107    $ref: /schemas/types.yaml#/definitions/uint32
108
109  clocks:
110    minItems: 1
111    maxItems: 2
112
113  clock-names:
114    description: List of names for the GIC clock input(s). Valid clock names
115      depend on the GIC variant.
116    oneOf:
117      - const: ic_clk # for "arm,arm11mp-gic"
118      - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
119      - items: # for "arm,cortex-a9-gic"
120          - const: PERIPHCLK
121          - const: PERIPHCLKEN
122      - const: clk # for "arm,gic-400" and "nvidia,tegra210"
123      - const: gclk #for "arm,pl390"
124
125  power-domains:
126    maxItems: 1
127
128required:
129  - compatible
130  - reg
131
132patternProperties:
133  "^v2m@[0-9a-f]+$":
134    type: object
135    description: |
136      * GICv2m extension for MSI/MSI-x support (Optional)
137
138      Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
139      This is enabled by specifying v2m sub-node(s).
140
141    properties:
142      compatible:
143        const: arm,gic-v2m-frame
144
145      msi-controller: true
146
147      reg:
148        maxItems: 1
149        description: GICv2m MSI interface register base and size
150
151      arm,msi-base-spi:
152        description: When the MSI_TYPER register contains an incorrect value,
153          this property should contain the SPI base of the MSI frame, overriding
154          the HW value.
155        $ref: /schemas/types.yaml#/definitions/uint32
156
157      arm,msi-num-spis:
158        description: When the MSI_TYPER register contains an incorrect value,
159          this property should contain the number of SPIs assigned to the
160          frame, overriding the HW value.
161        $ref: /schemas/types.yaml#/definitions/uint32
162
163    required:
164      - compatible
165      - msi-controller
166      - reg
167
168    additionalProperties: false
169
170additionalProperties: false
171
172examples:
173  - |
174    // GICv1
175    intc: interrupt-controller@fff11000 {
176      compatible = "arm,cortex-a9-gic";
177      #interrupt-cells = <3>;
178      #address-cells = <1>;
179      interrupt-controller;
180      reg = <0xfff11000 0x1000>,
181            <0xfff10100 0x100>;
182    };
183
184  - |
185    // GICv2
186    interrupt-controller@2c001000 {
187      compatible = "arm,cortex-a15-gic";
188      #interrupt-cells = <3>;
189      interrupt-controller;
190      reg = <0x2c001000 0x1000>,
191            <0x2c002000 0x2000>,
192            <0x2c004000 0x2000>,
193            <0x2c006000 0x2000>;
194      interrupts = <1 9 0xf04>;
195    };
196
197  - |
198    // GICv2m extension for MSI/MSI-x support
199    interrupt-controller@e1101000 {
200      compatible = "arm,gic-400";
201      #interrupt-cells = <3>;
202      #address-cells = <1>;
203      #size-cells = <1>;
204      interrupt-controller;
205      interrupts = <1 8 0xf04>;
206      ranges = <0 0xe1100000 0x100000>;
207      reg = <0xe1110000 0x01000>,
208            <0xe112f000 0x02000>,
209            <0xe1140000 0x10000>,
210            <0xe1160000 0x10000>;
211
212      v2m0: v2m@80000 {
213        compatible = "arm,gic-v2m-frame";
214        msi-controller;
215        reg = <0x80000 0x1000>;
216      };
217
218      //...
219
220      v2mN: v2m@90000 {
221        compatible = "arm,gic-v2m-frame";
222        msi-controller;
223        reg = <0x90000 0x1000>;
224      };
225    };
226...
227