1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Generic Interrupt Controller v1 and v2
8
9maintainers:
10  - Marc Zyngier <marc.zyngier@arm.com>
11
12description: |+
13  ARM SMP cores are often associated with a GIC, providing per processor
14  interrupts (PPI), shared processor interrupts (SPI) and software
15  generated interrupts (SGI).
16
17  Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
18  Secondary GICs are cascaded into the upward interrupt controller and do not
19  have PPIs or SGIs.
20
21allOf:
22  - $ref: /schemas/interrupt-controller.yaml#
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - arm,arm11mp-gic
30              - arm,cortex-a15-gic
31              - arm,cortex-a7-gic
32              - arm,cortex-a5-gic
33              - arm,cortex-a9-gic
34              - arm,eb11mp-gic
35              - arm,gic-400
36              - arm,pl390
37              - arm,tc11mp-gic
38              - nvidia,tegra210-agic
39              - qcom,msm-8660-qgic
40              - qcom,msm-qgic2
41
42      - items:
43          - const: arm,gic-400
44          - enum:
45             - arm,cortex-a15-gic
46             - arm,cortex-a7-gic
47
48      - items:
49          - const: arm,arm1176jzf-devchip-gic
50          - const: arm,arm11mp-gic
51
52      - items:
53          - const: brcm,brahma-b15-gic
54          - const: arm,cortex-a15-gic
55
56  interrupt-controller: true
57
58  "#address-cells":
59    enum: [ 0, 1 ]
60  "#size-cells":
61    const: 1
62
63  "#interrupt-cells":
64    const: 3
65    description: |
66      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
67      interrupts.
68
69      The 2nd cell contains the interrupt number for the interrupt type.
70      SPI interrupts are in the range [0-987].  PPI interrupts are in the
71      range [0-15].
72
73      The 3rd cell is the flags, encoded as follows:
74        bits[3:0] trigger type and level flags.
75          1 = low-to-high edge triggered
76          2 = high-to-low edge triggered (invalid for SPIs)
77          4 = active high level-sensitive
78          8 = active low level-sensitive (invalid for SPIs).
79        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
80        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
81        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
82        Also note that the configurability of PPI interrupts is IMPLEMENTATION
83        DEFINED and as such not guaranteed to be present (most SoC available
84        in 2014 seem to ignore the setting of this flag and use the hardware
85        default value).
86
87  reg:
88    description: |
89      Specifies base physical address(s) and size of the GIC registers. The
90      first region is the GIC distributor register base and size. The 2nd region
91      is the GIC cpu interface register base and size.
92
93      For GICv2 with virtualization extensions, additional regions are
94      required for specifying the base physical address and size of the VGIC
95      registers. The first additional region is the GIC virtual interface
96      control register base and size. The 2nd additional region is the GIC
97      virtual cpu interface register base and size.
98    minItems: 2
99    maxItems: 4
100
101  ranges: true
102
103  interrupts:
104    description: Interrupt source of the parent interrupt controller on
105      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
106      below).
107    maxItems: 1
108
109  cpu-offset:
110    description: per-cpu offset within the distributor and cpu interface
111      regions, used when the GIC doesn't have banked registers. The offset
112      is cpu-offset * cpu-nr.
113    $ref: /schemas/types.yaml#/definitions/uint32
114
115  clocks:
116    minItems: 1
117    maxItems: 2
118
119  clock-names:
120    description: List of names for the GIC clock input(s). Valid clock names
121      depend on the GIC variant.
122    oneOf:
123      - const: ic_clk # for "arm,arm11mp-gic"
124      - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
125      - items: # for "arm,cortex-a9-gic"
126          - const: PERIPHCLK
127          - const: PERIPHCLKEN
128      - const: clk # for "arm,gic-400" and "nvidia,tegra210"
129      - const: gclk #for "arm,pl390"
130
131  power-domains:
132    maxItems: 1
133
134required:
135  - compatible
136  - reg
137
138patternProperties:
139  "^v2m@[0-9a-f]+$":
140    type: object
141    description: |
142      * GICv2m extension for MSI/MSI-x support (Optional)
143
144      Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
145      This is enabled by specifying v2m sub-node(s).
146
147    properties:
148      compatible:
149        const: arm,gic-v2m-frame
150
151      msi-controller: true
152
153      reg:
154        maxItems: 1
155        description: GICv2m MSI interface register base and size
156
157      arm,msi-base-spi:
158        description: When the MSI_TYPER register contains an incorrect value,
159          this property should contain the SPI base of the MSI frame, overriding
160          the HW value.
161        $ref: /schemas/types.yaml#/definitions/uint32
162
163      arm,msi-num-spis:
164        description: When the MSI_TYPER register contains an incorrect value,
165          this property should contain the number of SPIs assigned to the
166          frame, overriding the HW value.
167        $ref: /schemas/types.yaml#/definitions/uint32
168
169    required:
170      - compatible
171      - msi-controller
172      - reg
173
174    additionalProperties: false
175
176additionalProperties: false
177
178examples:
179  - |
180    // GICv1
181    intc: interrupt-controller@fff11000 {
182      compatible = "arm,cortex-a9-gic";
183      #interrupt-cells = <3>;
184      #address-cells = <1>;
185      interrupt-controller;
186      reg = <0xfff11000 0x1000>,
187            <0xfff10100 0x100>;
188    };
189
190  - |
191    // GICv2
192    interrupt-controller@2c001000 {
193      compatible = "arm,cortex-a15-gic";
194      #interrupt-cells = <3>;
195      interrupt-controller;
196      reg = <0x2c001000 0x1000>,
197            <0x2c002000 0x2000>,
198            <0x2c004000 0x2000>,
199            <0x2c006000 0x2000>;
200      interrupts = <1 9 0xf04>;
201    };
202
203  - |
204    // GICv2m extension for MSI/MSI-x support
205    interrupt-controller@e1101000 {
206      compatible = "arm,gic-400";
207      #interrupt-cells = <3>;
208      #address-cells = <1>;
209      #size-cells = <1>;
210      interrupt-controller;
211      interrupts = <1 8 0xf04>;
212      ranges = <0 0xe1100000 0x100000>;
213      reg = <0xe1110000 0x01000>,
214            <0xe112f000 0x02000>,
215            <0xe1140000 0x10000>,
216            <0xe1160000 0x10000>;
217
218      v2m0: v2m@80000 {
219        compatible = "arm,gic-v2m-frame";
220        msi-controller;
221        reg = <0x80000 0x1000>;
222      };
223
224      //...
225
226      v2mN: v2m@90000 {
227        compatible = "arm,gic-v2m-frame";
228        msi-controller;
229        reg = <0x90000 0x1000>;
230      };
231    };
232...
233