1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Generic Interrupt Controller v1 and v2
8
9maintainers:
10  - Marc Zyngier <marc.zyngier@arm.com>
11
12description: |+
13  ARM SMP cores are often associated with a GIC, providing per processor
14  interrupts (PPI), shared processor interrupts (SPI) and software
15  generated interrupts (SGI).
16
17  Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
18  Secondary GICs are cascaded into the upward interrupt controller and do not
19  have PPIs or SGIs.
20
21allOf:
22  - $ref: /schemas/interrupt-controller.yaml#
23
24properties:
25  compatible:
26    oneOf:
27      - items:
28          - enum:
29              - arm,arm11mp-gic
30              - arm,cortex-a15-gic
31              - arm,cortex-a7-gic
32              - arm,cortex-a5-gic
33              - arm,cortex-a9-gic
34              - arm,eb11mp-gic
35              - arm,gic-400
36              - arm,pl390
37              - arm,tc11mp-gic
38              - nvidia,tegra210-agic
39              - qcom,msm-8660-qgic
40              - qcom,msm-qgic2
41
42      - items:
43          - const: arm,arm1176jzf-devchip-gic
44          - const: arm,arm11mp-gic
45
46      - items:
47          - const: brcm,brahma-b15-gic
48          - const: arm,cortex-a15-gic
49
50  interrupt-controller: true
51
52  "#address-cells":
53    enum: [ 0, 1 ]
54  "#size-cells":
55    const: 1
56
57  "#interrupt-cells":
58    const: 3
59    description: |
60      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
61      interrupts.
62
63      The 2nd cell contains the interrupt number for the interrupt type.
64      SPI interrupts are in the range [0-987].  PPI interrupts are in the
65      range [0-15].
66
67      The 3rd cell is the flags, encoded as follows:
68        bits[3:0] trigger type and level flags.
69          1 = low-to-high edge triggered
70          2 = high-to-low edge triggered (invalid for SPIs)
71          4 = active high level-sensitive
72          8 = active low level-sensitive (invalid for SPIs).
73        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
74        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
75        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
76        Also note that the configurability of PPI interrupts is IMPLEMENTATION
77        DEFINED and as such not guaranteed to be present (most SoC available
78        in 2014 seem to ignore the setting of this flag and use the hardware
79        default value).
80
81  reg:
82    description: |
83      Specifies base physical address(s) and size of the GIC registers. The
84      first region is the GIC distributor register base and size. The 2nd region
85      is the GIC cpu interface register base and size.
86
87      For GICv2 with virtualization extensions, additional regions are
88      required for specifying the base physical address and size of the VGIC
89      registers. The first additional region is the GIC virtual interface
90      control register base and size. The 2nd additional region is the GIC
91      virtual cpu interface register base and size.
92    minItems: 2
93    maxItems: 4
94
95  interrupts:
96    description: Interrupt source of the parent interrupt controller on
97      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
98      below).
99    maxItems: 1
100
101  cpu-offset:
102    description: per-cpu offset within the distributor and cpu interface
103      regions, used when the GIC doesn't have banked registers. The offset
104      is cpu-offset * cpu-nr.
105    $ref: /schemas/types.yaml#/definitions/uint32
106
107  clocks:
108    minItems: 1
109    maxItems: 2
110
111  clock-names:
112    description: List of names for the GIC clock input(s). Valid clock names
113      depend on the GIC variant.
114    oneOf:
115      - const: ic_clk # for "arm,arm11mp-gic"
116      - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
117      - items: # for "arm,cortex-a9-gic"
118          - const: PERIPHCLK
119          - const: PERIPHCLKEN
120      - const: clk # for "arm,gic-400" and "nvidia,tegra210"
121      - const: gclk #for "arm,pl390"
122
123  power-domains:
124    maxItems: 1
125
126required:
127  - compatible
128  - reg
129
130patternProperties:
131  "^v2m@[0-9a-f]+$":
132    type: object
133    description: |
134      * GICv2m extension for MSI/MSI-x support (Optional)
135
136      Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
137      This is enabled by specifying v2m sub-node(s).
138
139    properties:
140      compatible:
141        const: arm,gic-v2m-frame
142
143      msi-controller: true
144
145      reg:
146        maxItems: 1
147        description: GICv2m MSI interface register base and size
148
149      arm,msi-base-spi:
150        description: When the MSI_TYPER register contains an incorrect value,
151          this property should contain the SPI base of the MSI frame, overriding
152          the HW value.
153        $ref: /schemas/types.yaml#/definitions/uint32
154
155      arm,msi-num-spis:
156        description: When the MSI_TYPER register contains an incorrect value,
157          this property should contain the number of SPIs assigned to the
158          frame, overriding the HW value.
159        $ref: /schemas/types.yaml#/definitions/uint32
160
161    required:
162      - compatible
163      - msi-controller
164      - reg
165
166    additionalProperties: false
167
168additionalProperties: false
169
170examples:
171  - |
172    // GICv1
173    intc: interrupt-controller@fff11000 {
174      compatible = "arm,cortex-a9-gic";
175      #interrupt-cells = <3>;
176      #address-cells = <1>;
177      interrupt-controller;
178      reg = <0xfff11000 0x1000>,
179            <0xfff10100 0x100>;
180    };
181
182  - |
183    // GICv2
184    interrupt-controller@2c001000 {
185      compatible = "arm,cortex-a15-gic";
186      #interrupt-cells = <3>;
187      interrupt-controller;
188      reg = <0x2c001000 0x1000>,
189            <0x2c002000 0x2000>,
190            <0x2c004000 0x2000>,
191            <0x2c006000 0x2000>;
192      interrupts = <1 9 0xf04>;
193    };
194
195  - |
196    // GICv2m extension for MSI/MSI-x support
197    interrupt-controller@e1101000 {
198      compatible = "arm,gic-400";
199      #interrupt-cells = <3>;
200      #address-cells = <2>;
201      #size-cells = <2>;
202      interrupt-controller;
203      interrupts = <1 8 0xf04>;
204      ranges = <0 0 0 0xe1100000 0 0x100000>;
205      reg = <0x0 0xe1110000 0 0x01000>,
206            <0x0 0xe112f000 0 0x02000>,
207            <0x0 0xe1140000 0 0x10000>,
208            <0x0 0xe1160000 0 0x10000>;
209
210      v2m0: v2m@8000 {
211        compatible = "arm,gic-v2m-frame";
212        msi-controller;
213        reg = <0x0 0x80000 0 0x1000>;
214      };
215
216      //...
217
218      v2mN: v2m@9000 {
219        compatible = "arm,gic-v2m-frame";
220        msi-controller;
221        reg = <0x0 0x90000 0 0x1000>;
222      };
223    };
224...
225