1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Apple Interrupt Controller 2
8
9maintainers:
10  - Hector Martin <marcan@marcan.st>
11
12description: |
13  The Apple Interrupt Controller 2 is a simple interrupt controller present on
14  Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
15
16  It provides the following features:
17
18  - Level-triggered hardware IRQs wired to SoC blocks
19    - Single mask bit per IRQ
20    - Automatic masking on event delivery (auto-ack)
21    - Software triggering (ORed with hw line)
22  - Automatic prioritization (single event/ack register per CPU, lower IRQs =
23    higher priority)
24  - Automatic masking on ack
25  - Support for multiple dies
26
27  This device also represents the FIQ interrupt sources on platforms using AIC,
28  which do not go through a discrete interrupt controller. It also handles
29  FIQ-based Fast IPIs.
30
31properties:
32  compatible:
33    items:
34      - const: apple,t6000-aic
35      - const: apple,aic2
36
37  interrupt-controller: true
38
39  '#interrupt-cells':
40    const: 4
41    description: |
42      The 1st cell contains the interrupt type:
43        - 0: Hardware IRQ
44        - 1: FIQ
45
46      The 2nd cell contains the die ID.
47
48      The next cell contains the interrupt number.
49        - HW IRQs: interrupt number
50        - FIQs:
51          - 0: physical HV timer
52          - 1: virtual HV timer
53          - 2: physical guest timer
54          - 3: virtual guest timer
55
56      The last cell contains the interrupt flags. This is normally
57      IRQ_TYPE_LEVEL_HIGH (4).
58
59  reg:
60    items:
61      - description: Address and size of the main AIC2 registers.
62      - description: Address and size of the AIC2 Event register.
63
64  reg-names:
65    items:
66      - const: core
67      - const: event
68
69  power-domains:
70    maxItems: 1
71
72  affinities:
73    type: object
74    additionalProperties: false
75    description:
76      FIQ affinity can be expressed as a single "affinities" node,
77      containing a set of sub-nodes, one per FIQ with a non-default
78      affinity.
79    patternProperties:
80      "^.+-affinity$":
81        type: object
82        additionalProperties: false
83        properties:
84          apple,fiq-index:
85            description:
86              The interrupt number specified as a FIQ, and for which
87              the affinity is not the default.
88            $ref: /schemas/types.yaml#/definitions/uint32
89            maximum: 5
90
91          cpus:
92            $ref: /schemas/types.yaml#/definitions/phandle-array
93            description:
94              Should be a list of phandles to CPU nodes (as described in
95              Documentation/devicetree/bindings/arm/cpus.yaml).
96
97        required:
98          - apple,fiq-index
99          - cpus
100
101required:
102  - compatible
103  - '#interrupt-cells'
104  - interrupt-controller
105  - reg
106  - reg-names
107
108additionalProperties: false
109
110allOf:
111  - $ref: /schemas/interrupt-controller.yaml#
112
113examples:
114  - |
115    soc {
116        #address-cells = <2>;
117        #size-cells = <2>;
118
119        aic: interrupt-controller@28e100000 {
120            compatible = "apple,t6000-aic", "apple,aic2";
121            #interrupt-cells = <4>;
122            interrupt-controller;
123            reg = <0x2 0x8e100000 0x0 0xc000>,
124                  <0x2 0x8e10c000 0x0 0x4>;
125            reg-names = "core", "event";
126        };
127    };
128